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| author | Tom Rini <trini@ti.com> | 2012-10-04 10:00:42 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-04 10:00:42 -0700 |
| commit | 198166877768cf4d0197289a524df8a6ca0e2f19 (patch) | |
| tree | d8fb2afc6d5b09ceeb4e3e62dc20b64d167ab346 /arch/arm/include/asm/arch-socfpga/reset_manager.h | |
| parent | 73c15c634dda388e21eaf0ebc85e324872df0d25 (diff) | |
| parent | 777544085d2b417a36df50eb564bf037a044e60e (diff) | |
| download | olio-uboot-2014.01-198166877768cf4d0197289a524df8a6ca0e2f19.tar.xz olio-uboot-2014.01-198166877768cf4d0197289a524df8a6ca0e2f19.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm/arch-socfpga/reset_manager.h')
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/reset_manager.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 000000000..d9d2c1c56 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ |