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| author | Heiko Schocher <hs@denx.de> | 2011-09-14 19:59:33 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-30 22:00:58 +0200 |
| commit | b841c01d6a9c00ea1a4168b30ad4d6f45b4e519e (patch) | |
| tree | aa98e0b50eb66ddee1c9b48d6e47043c61c6dd61 /arch/arm/include/asm/arch-davinci/hardware.h | |
| parent | 41d272d1efa2c54ed81bfb701d1960691bb4eb0d (diff) | |
| download | olio-uboot-2014.01-b841c01d6a9c00ea1a4168b30ad4d6f45b4e519e.tar.xz olio-uboot-2014.01-b841c01d6a9c00ea1a4168b30ad4d6f45b4e519e.zip | |
arm, davinci: add SYSCFG1 base and register struct
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-davinci/hardware.h')
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/hardware.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 19ab68075..dcc71d609 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -142,6 +142,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_SYSCFG1_BASE 0x01e2c000 #define DAVINCI_MMC_SD0_BASE 0x01c40000 #define DAVINCI_MMC_SD1_BASE 0x01e1b000 #define DAVINCI_TIMER2_BASE 0x01f0c000 @@ -448,6 +449,21 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) +struct davinci_syscfg1_regs { + dv_reg vtpio_ctl; + dv_reg ddr_slew; + dv_reg deepsleep; + dv_reg pupd_ena; + dv_reg pupd_sel; + dv_reg rxactive; + dv_reg pwrdwn; +}; + +#define davinci_syscfg1_regs \ + ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) + +#define DDR_SLEW_CMOSEN_BIT 4 + /* Interrupt controller */ struct davinci_aintc_regs { dv_reg revid; |