Merge branch 'master' of git://88.191.163.10/u-boot-arm

Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.

Conflicts:
	arch/arm/include/asm/arch-am33xx/hardware.h

Signed-off-by: Tom Rini <trini@ti.com>

28 files changed, 1097 insertions, 698 deletions

diff --git a/arch/arm/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile
deleted file mode 100644
index 7d76d96ca..000000000
--- a/arch/arm/cpu/arm1136/omap24xx/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= reset.o
-
-COBJS	= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S
deleted file mode 100644
index dd0752b28..000000000
--- a/arch/arm/cpu/arm1136/omap24xx/reset.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+ 
- */
-
-#include <asm/arch/omap2420.h>
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl	/* get addr for global reset reg */
-	mov	r3, #0x2	/* full reset pll+mpu */
-	str	r3, [r1]	/* force reset */
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PM_RSTCTRL_WKUP
diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c
deleted file mode 100644
index b1eef27da..000000000
--- a/arch/arm/cpu/arm1136/omap24xx/timer.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
-
-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL 0
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER	readl(CONFIG_SYS_TIMERBASE+TCRR) \
-			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
-	int32_t val;
-
-	/* Start the counter ticking up */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
-	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
-
-	/* reset time */
-	gd->arch.lastinc = READ_TIMER;	/* capture current incrementer value */
-	gd->arch.tbl = 0;		/* start "advancing" time stamp */
-
-	return(0);
-}
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if ((tmo + tmp + 1) < tmp) {	/* if setting this forward will roll */
-					/* time stamp, then reset time */
-		gd->arch.lastinc = READ_TIMER;	/* capture incrementer value */
-		gd->arch.tbl = 0;			/* start time stamp */
-	} else {
-		tmo	+= tmp;		/* else, set advancing stamp wake up time */
-	}
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (now >= gd->arch.lastinc) {		/* normal mode (non roll) */
-		/* move stamp fordward with absoulte diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ))
-				 - gd->arch.lastinc) + now;
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;			/* finish normalize. */
-	} else {					/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index f6bf1ef8c..a3bbbb869 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -299,7 +299,11 @@ int arch_cpu_init(void)
 	 */
 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
+#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
+#else
 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+#endif
 
 #if defined(CONFIG_SYS_DA850_DDR_INIT)
 	da850_ddr_setup();
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index f603f2fe9..6105f6390 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -28,6 +28,11 @@ const struct pinmux_config uart0_pins_txrx[] = {
 	{ pinmux(3), 2, 5 }, /* UART0_TXD */
 };
 
+const struct pinmux_config uart0_pins_rtscts[] = {
+	{ pinmux(3), 2, 6 },
+	{ pinmux(3), 2, 7 },
+};
+
 const struct pinmux_config uart1_pins_txrx[] = {
 	{ pinmux(4), 2, 6 }, /* UART1_RXD */
 	{ pinmux(4), 2, 7 }, /* UART1_TXD */
@@ -51,6 +56,7 @@ const struct pinmux_config emac_pins_rmii[] = {
 	{ pinmux(14), 8, 5 }, /* RMII_RXD[1] */
 	{ pinmux(14), 8, 6 }, /* RMII_RXD[0] */
 	{ pinmux(14), 8, 7 }, /* RMII_RXER */
+	{ pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
 	{ pinmux(15), 8, 1 }, /* RMII_CRS_DV */
 };
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 2ba88d0a9..b723e22a5 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -16,7 +16,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index dbd1ec3c0..f6a297c9d 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -10,6 +10,13 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_AM33XX)	+= clock_am33xx.o
 COBJS-$(CONFIG_TI814X)	+= clock_ti814x.o
+COBJS-$(CONFIG_AM43XX)	+= clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+COBJS	+= clock.o
+endif
+
+COBJS-$(CONFIG_TI816X)	+= clock_ti816x.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 07ab91c3e..2ea3d698f 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void setup_clocks_for_console(void)
-{
-	/* Not yet implemented */
-	return;
-}
-
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
@@ -142,8 +136,8 @@ int arch_misc_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
-void rtc32k_enable(void)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+static void rtc32k_enable(void)
 {
 	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
@@ -159,11 +153,7 @@ void rtc32k_enable(void)
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
 
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
 {
 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 	u32 regval;
@@ -180,4 +170,58 @@ void uart_soft_reset(void)
 	regval |= UART_SMART_IDLE_EN;
 	writel(regval, &uart_base->uartsyscfg);
 }
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+#endif
+
+void s_init(void)
+{
+	/*
+	 * The ROM will only have set up sufficient pinmux to allow for the
+	 * first 4KiB NOR to be read, we must finish doing what we know of
+	 * the NOR mux in this space in order to continue.
+	 */
+#ifdef CONFIG_NOR_BOOT
+	enable_norboot_pin_mux();
+#endif
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+	watchdog_disable();
+	timer_init();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
 #endif
+#ifdef CONFIG_NOR_BOOT
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+#else
+	gd = &gdata;
+	preloader_console_init();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+	prcm_init();
+	set_mux_conf_regs();
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+	sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000000000..8e5f3c671
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,171 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+			 const struct dpll_params *params)
+{
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+		hang();
+	}
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("Bypassing DPLL failed 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+	}
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	do_bypass_dpll(dpll_regs);
+	wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+		   const struct dpll_params *params)
+{
+	u32 temp;
+
+	if (!params)
+		return;
+
+	temp = readl(dpll_regs->cm_clksel_dpll);
+
+	bypass_dpll(dpll_regs);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, dpll_regs->cm_clksel_dpll);
+
+	setup_post_dividers(dpll_regs, params);
+
+	/* Wait till the DPLL locks */
+	do_lock_dpll(dpll_regs);
+	wait_for_lock(dpll_regs);
+}
+
+static void setup_dplls(void)
+{
+	const struct dpll_params *params;
+	do_setup_dpll(&dpll_core_regs, &dpll_core);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
+	do_setup_dpll(&dpll_per_regs, &dpll_per);
+	writel(0x300, &cmwkup->clkdcoldodpllper);
+
+	params = get_dpll_ddr_params();
+	do_setup_dpll(&dpll_ddr_regs, params);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				       u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %p\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+}
+
+void prcm_init()
+{
+	enable_basic_clocks();
+	setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fb3fb43dc..e5f287b33 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -14,392 +14,129 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-#define PRCM_MOD_EN		0x2
-#define PRCM_FORCE_WAKEUP	0x2
-#define PRCM_FUNCTL		0x0
-
-#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
-#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
-
-#define PLL_BYPASS_MODE		0x4
-#define ST_MN_BYPASS		0x00000100
-#define ST_DPLL_CLK		0x00000001
-#define CLK_SEL_MASK		0x7ffff
-#define CLK_DIV_MASK		0x1f
-#define CLK_DIV2_MASK		0x7f
-#define CLK_SEL_SHIFT		0x8
-#define CLK_MODE_SEL		0x7
-#define CLK_MODE_MASK		0xfffffff8
-#define CLK_DIV_SEL		0xFFFFFFE0
-#define CPGMAC0_IDLE		0x30000
-#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
-
 #define OSC	(V_OSCK/1000000)
 
-#define MPUPLL_M	CONFIG_SYS_MPUCLK
-#define MPUPLL_N	(OSC-1)
-#define MPUPLL_M2	1
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000
-#define COREPLL_N	(OSC-1)
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x88,
+	.cm_idlest_dpll		= CM_WKUP + 0x20,
+	.cm_clksel_dpll		= CM_WKUP + 0x2C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA8,
+};
 
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x90,
+	.cm_idlest_dpll		= CM_WKUP + 0x5C,
+	.cm_clksel_dpll		= CM_WKUP + 0x68,
+	.cm_div_m4_dpll		= CM_WKUP + 0x80,
+	.cm_div_m5_dpll		= CM_WKUP + 0x84,
+	.cm_div_m6_dpll		= CM_WKUP + 0xD8,
+};
 
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_N	(OSC-1)
-#define PERPLL_M2	5
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x8C,
+	.cm_idlest_dpll		= CM_WKUP + 0x70,
+	.cm_clksel_dpll		= CM_WKUP + 0x9C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xAC,
+};
 
-/* DDR Freq is 266 MHZ for now */
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M	266
-#define DDRPLL_N	(OSC-1)
-#define DDRPLL_M2	1
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x94,
+	.cm_idlest_dpll		= CM_WKUP + 0x34,
+	.cm_clksel_dpll		= CM_WKUP + 0x40,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
+};
 
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+const struct dpll_params dpll_mpu = {
+		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_per = {
+		960, OSC-1, 5, -1, -1, -1, -1};
 
-static void enable_interface_clocks(void)
+void setup_clocks_for_console(void)
 {
-	/* Enable all the Interconnect Modules */
-	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
-	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
-	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
-		;
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
-	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
-	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
-		;
+	clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
-	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
-	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
-	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
-	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
-	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
-		;
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart1clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart2clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart3clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart4clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart5clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
+void enable_basic_clocks(void)
 {
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
-}
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l4fwclkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emiffwclkctrl,
+		&cmrtc->clkstctrl,
+		0
+	};
 
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
-	/* Enable the control module though RBL would have done it*/
-	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
-	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
-		;
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
+		&cmper->spi0clkctrl,
+		&cmrtc->rtcclkctrl,
+		&cmper->usb0clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		0
+	};
 
-	/* Enable the module clock */
-	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
-	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
-		;
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
-
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
-	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* UART1 */
-#ifdef CONFIG_SERIAL2
-	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
-	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL2 */
-
-	/* UART2 */
-#ifdef CONFIG_SERIAL3
-	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
-	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL3 */
-
-	/* UART3 */
-#ifdef CONFIG_SERIAL4
-	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
-	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL4 */
-
-	/* UART4 */
-#ifdef CONFIG_SERIAL5
-	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
-	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL5 */
-
-	/* UART5 */
-#ifdef CONFIG_SERIAL6
-	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
-	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL6 */
-
-	/* GPMC */
-	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
-	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* ELM */
-	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
-	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MMC0*/
-	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
-	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MMC1 */
-	writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
-	while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
-	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio1 module */
-	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
-	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio2 module */
-	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
-	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio3 module */
-	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
-	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c1 */
-	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
-	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Ethernet */
-	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
-	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
-		;
-
-	/* spi0 */
-	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
-	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* RTC */
-	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
-	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MUSB */
-	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
-	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
-		;
-}
-
-void mpu_pll_config_val(int mpull_m)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllmpu);
-	clksel = readl(&cmwkup->clkseldpllmpu);
-	div_m2 = readl(&cmwkup->divm2dpllmpu);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
-	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
-	writel(clksel, &cmwkup->clkseldpllmpu);
-
-	div_m2 = div_m2 & ~CLK_DIV_MASK;
-	div_m2 = div_m2 | MPUPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllmpu);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllmpu);
-
-	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
-		;
-}
-
-static void mpu_pll_config(void)
-{
-	mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
-{
-	u32 clkmode, clksel, div_m4, div_m5, div_m6;
-
-	clkmode = readl(&cmwkup->clkmoddpllcore);
-	clksel = readl(&cmwkup->clkseldpllcore);
-	div_m4 = readl(&cmwkup->divm4dpllcore);
-	div_m5 = readl(&cmwkup->divm5dpllcore);
-	div_m6 = readl(&cmwkup->divm6dpllcore);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
-	writel(clksel, &cmwkup->clkseldpllcore);
-
-	div_m4 = div_m4 & ~CLK_DIV_MASK;
-	div_m4 = div_m4 | COREPLL_M4;
-	writel(div_m4, &cmwkup->divm4dpllcore);
-
-	div_m5 = div_m5 & ~CLK_DIV_MASK;
-	div_m5 = div_m5 | COREPLL_M5;
-	writel(div_m5, &cmwkup->divm5dpllcore);
-
-	div_m6 = div_m6 & ~CLK_DIV_MASK;
-	div_m6 = div_m6 | COREPLL_M6;
-	writel(div_m6, &cmwkup->divm6dpllcore);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
-		;
-}
-
-static void per_pll_config(void)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllper);
-	clksel = readl(&cmwkup->clkseldpllper);
-	div_m2 = readl(&cmwkup->divm2dpllper);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
-	writel(clksel, &cmwkup->clkseldpllper);
-
-	div_m2 = div_m2 & ~CLK_DIV2_MASK;
-	div_m2 = div_m2 | PERPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllper);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
-		;
-
-	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllddr);
-	clksel = readl(&cmwkup->clkseldpllddr);
-	div_m2 = readl(&cmwkup->divm2dpllddr);
-
-	/* Set the PLL to bypass Mode */
-	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till bypass mode is enabled */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
-				!= ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
-	writel(clksel, &cmwkup->clkseldpllddr);
-
-	div_m2 = div_m2 & CLK_DIV_SEL;
-	div_m2 = div_m2 | DDRPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllddr);
-
-	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till dpll is locked */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	/* Enable the  EMIF_FW Functional clock */
-	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
-	/* Enable EMIF0 Clock */
-	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-	/* Poll if module is functional */
-	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
-		;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
-	mpu_pll_config();
-	core_pll_config();
-	per_pll_config();
-
-	/* Enable the required interconnect clocks */
-	enable_interface_clocks();
-
-	/* Power domain wake up transition */
-	power_domain_wkup_transition();
-
-	/* Enable the required peripherals */
-	enable_per_clocks();
 }
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
new file mode 100644
index 000000000..c4890f2b4
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -0,0 +1,110 @@
+/*
+ * clock_am43xx.c
+ *
+ * clocks for AM43XX based boards
+ * Derived from AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x560,
+	.cm_idlest_dpll		= CM_WKUP + 0x564,
+	.cm_clksel_dpll		= CM_WKUP + 0x56c,
+	.cm_div_m2_dpll		= CM_WKUP + 0x570,
+};
+
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x520,
+	.cm_idlest_dpll		= CM_WKUP + 0x524,
+	.cm_clksel_dpll		= CM_WKUP + 0x52C,
+	.cm_div_m4_dpll		= CM_WKUP + 0x538,
+	.cm_div_m5_dpll		= CM_WKUP + 0x53C,
+	.cm_div_m6_dpll		= CM_WKUP + 0x540,
+};
+
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x5E0,
+	.cm_idlest_dpll		= CM_WKUP + 0x5E4,
+	.cm_clksel_dpll		= CM_WKUP + 0x5EC,
+	.cm_div_m2_dpll		= CM_WKUP + 0x5F0,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x5A0,
+	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
+	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
+	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
+};
+
+const struct dpll_params dpll_mpu = {
+		-1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		-1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params dpll_per = {
+		-1, -1, -1, -1, -1, -1, -1};
+
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable UART0 */
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emifclkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		&cmper->otfaemifclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 658772bbe..ef14f47eb 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -100,103 +100,8 @@ struct ad_pll {
 
 #define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
 
-/* PRCM */
 #define ENET_CLKCTRL_CMPL		0x30000
 
-#define CM_DEFAULT_BASE			(PRCM_BASE + 0x0500)
-
-struct cm_def {
-	unsigned int resv0[2];
-	unsigned int l3fastclkstctrl;
-	unsigned int resv1[1];
-	unsigned int pciclkstctrl;
-	unsigned int resv2[1];
-	unsigned int ducaticlkstctrl;
-	unsigned int resv3[1];
-	unsigned int emif0clkctrl;
-	unsigned int emif1clkctrl;
-	unsigned int dmmclkctrl;
-	unsigned int fwclkctrl;
-	unsigned int resv4[10];
-	unsigned int usbclkctrl;
-	unsigned int resv5[1];
-	unsigned int sataclkctrl;
-	unsigned int resv6[4];
-	unsigned int ducaticlkctrl;
-	unsigned int pciclkctrl;
-};
-
-#define CM_ALWON_BASE			(PRCM_BASE + 0x1400)
-
-struct cm_alwon {
-	unsigned int l3slowclkstctrl;
-	unsigned int ethclkstctrl;
-	unsigned int l3medclkstctrl;
-	unsigned int mmu_clkstctrl;
-	unsigned int mmucfg_clkstctrl;
-	unsigned int ocmc0clkstctrl;
-	unsigned int vcpclkstctrl;
-	unsigned int mpuclkstctrl;
-	unsigned int sysclk4clkstctrl;
-	unsigned int sysclk5clkstctrl;
-	unsigned int sysclk6clkstctrl;
-	unsigned int rtcclkstctrl;
-	unsigned int l3fastclkstctrl;
-	unsigned int resv0[67];
-	unsigned int mcasp0clkctrl;
-	unsigned int mcasp1clkctrl;
-	unsigned int mcasp2clkctrl;
-	unsigned int mcbspclkctrl;
-	unsigned int uart0clkctrl;
-	unsigned int uart1clkctrl;
-	unsigned int uart2clkctrl;
-	unsigned int gpio0clkctrl;
-	unsigned int gpio1clkctrl;
-	unsigned int i2c0clkctrl;
-	unsigned int i2c1clkctrl;
-	unsigned int mcasp345clkctrl;
-	unsigned int atlclkctrl;
-	unsigned int mlbclkctrl;
-	unsigned int pataclkctrl;
-	unsigned int resv1[1];
-	unsigned int uart3clkctrl;
-	unsigned int uart4clkctrl;
-	unsigned int uart5clkctrl;
-	unsigned int wdtimerclkctrl;
-	unsigned int spiclkctrl;
-	unsigned int mailboxclkctrl;
-	unsigned int spinboxclkctrl;
-	unsigned int mmudataclkctrl;
-	unsigned int resv2[2];
-	unsigned int mmucfgclkctrl;
-	unsigned int resv3[2];
-	unsigned int ocmc0clkctrl;
-	unsigned int vcpclkctrl;
-	unsigned int resv4[2];
-	unsigned int controlclkctrl;
-	unsigned int resv5[2];
-	unsigned int gpmcclkctrl;
-	unsigned int ethernet0clkctrl;
-	unsigned int ethernet1clkctrl;
-	unsigned int mpuclkctrl;
-	unsigned int debugssclkctrl;
-	unsigned int l3clkctrl;
-	unsigned int l4hsclkctrl;
-	unsigned int l4lsclkctrl;
-	unsigned int rtcclkctrl;
-	unsigned int tpccclkctrl;
-	unsigned int tptc0clkctrl;
-	unsigned int tptc1clkctrl;
-	unsigned int tptc2clkctrl;
-	unsigned int tptc3clkctrl;
-	unsigned int resv7[4];
-	unsigned int dcan01clkctrl;
-	unsigned int mmchs0clkctrl;
-	unsigned int mmchs1clkctrl;
-	unsigned int mmchs2clkctrl;
-	unsigned int custefuseclkctrl;
-};
-
 #define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
 
 struct sata_pll {
@@ -264,11 +169,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
  */
 static void enable_per_clocks(void)
 {
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-		;
-
 	/* HSMMC1 */
 	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
 	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
@@ -282,6 +182,12 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
 	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
 		;
+
+	/* RTC clocks */
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+	while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+		;
 }
 
 /*
@@ -455,8 +361,6 @@ void sata_pll_config(void)
 		;
 }
 
-void enable_emif_clocks(void) {};
-
 void enable_dmm_clocks(void)
 {
 	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
@@ -477,13 +381,19 @@ void enable_dmm_clocks(void)
 		;
 }
 
+void setup_clocks_for_console(void)
+{
+	unlock_pll_control_mmr();
+	/* UART0 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+}
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */
-void pll_init()
+void prcm_init(void)
 {
-	unlock_pll_control_mmr();
-
 	/* Enable the control module */
 	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
new file mode 100644
index 000000000..ace4a5afe
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
@@ -0,0 +1,445 @@
+/*
+ * clock_ti816x.c
+ *
+ * Clocks for TI816X based boards
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#include <asm/emif.h>
+
+#define CM_PLL_BASE		(CTRL_BASE + 0x0400)
+
+/* Main PLL */
+#define MAIN_N			64
+#define MAIN_P			0x1
+#define MAIN_INTFREQ1		0x8
+#define MAIN_FRACFREQ1		0x800000
+#define MAIN_MDIV1		0x2
+#define MAIN_INTFREQ2		0xE
+#define MAIN_FRACFREQ2		0x0
+#define MAIN_MDIV2		0x1
+#define MAIN_INTFREQ3		0x8
+#define MAIN_FRACFREQ3		0xAAAAB0
+#define MAIN_MDIV3		0x3
+#define MAIN_INTFREQ4		0x9
+#define MAIN_FRACFREQ4		0x55554F
+#define MAIN_MDIV4		0x3
+#define MAIN_INTFREQ5		0x9
+#define MAIN_FRACFREQ5		0x374BC6
+#define MAIN_MDIV5		0xC
+#define MAIN_MDIV6		0x48
+#define MAIN_MDIV7		0x4
+
+/* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x4
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x3
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N			50
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x9
+#define DDR_FRACFREQ2		0x0
+#define DDR_MDIV2		0x19
+#define DDR_INTFREQ3		0x13
+#define DDR_FRACFREQ3		0x800000
+#define DDR_MDIV3		0x2
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+#define CONTROL_STATUS			(CTRL_BASE + 0x40)
+#define DDR_RCD				(CTRL_BASE + 0x070C)
+#define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
+#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
+
+#define INTCPS_SYSCONFIG	0x48200010
+#define CM_SYSCLK10_CLKSEL	0x48180324
+
+struct cm_pll {
+	unsigned int mainpll_ctrl;	/* offset 0x400 */
+	unsigned int mainpll_pwd;
+	unsigned int mainpll_freq1;
+	unsigned int mainpll_div1;
+	unsigned int mainpll_freq2;
+	unsigned int mainpll_div2;
+	unsigned int mainpll_freq3;
+	unsigned int mainpll_div3;
+	unsigned int mainpll_freq4;
+	unsigned int mainpll_div4;
+	unsigned int mainpll_freq5;
+	unsigned int mainpll_div5;
+	unsigned int resv0[1];
+	unsigned int mainpll_div6;
+	unsigned int resv1[1];
+	unsigned int mainpll_div7;
+	unsigned int ddrpll_ctrl;	/* offset 0x440 */
+	unsigned int ddrpll_pwd;
+	unsigned int resv2[1];
+	unsigned int ddrpll_div1;
+	unsigned int ddrpll_freq2;
+	unsigned int ddrpll_div2;
+	unsigned int ddrpll_freq3;
+	unsigned int ddrpll_div3;
+	unsigned int ddrpll_freq4;
+	unsigned int ddrpll_div4;
+	unsigned int ddrpll_freq5;
+	unsigned int ddrpll_div5;
+	unsigned int videopll_ctrl;	/* offset 0x470 */
+	unsigned int videopll_pwd;
+	unsigned int videopll_freq1;
+	unsigned int videopll_div1;
+	unsigned int videopll_freq2;
+	unsigned int videopll_div2;
+	unsigned int videopll_freq3;
+	unsigned int videopll_div3;
+	unsigned int resv3[4];
+	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
+	unsigned int audiopll_pwd;
+	unsigned int resv4[2];
+	unsigned int audiopll_freq2;
+	unsigned int audiopll_div2;
+	unsigned int audiopll_freq3;
+	unsigned int audiopll_div3;
+	unsigned int audiopll_freq4;
+	unsigned int audiopll_div4;
+	unsigned int audiopll_freq5;
+	unsigned int audiopll_div5;
+};
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
+const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+void enable_dmm_clocks(void)
+{
+	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+
+	/* Wait for clocks to be active */
+	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+		;
+	/* Wait for emif0 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
+		;
+	/* Wait for emif1 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
+		;
+
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	/* Wait for dmm to be fully functional, including OCP */
+	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
+		;
+
+	/* Enable Tiled Access */
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
+}
+
+/* assume delay is aprox at least 1us */
+static void ddr_delay(int d)
+{
+	int i;
+
+	/*
+	 * read a control register.
+	 * this is a bit more delay and cannot be optimized by the compiler
+	 * assuming one read takes 200 cycles and A8 is runing 1 GHz
+	 * somewhat conservative setting
+	 */
+	for (i = 0; i < 50*d; i++)
+		readl(CONTROL_STATUS);
+}
+
+static void main_pll_init_ti816x(void)
+{
+	u32 main_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	main_pll_ctrl |= BIT(2);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFF7;
+	main_pll_ctrl |= BIT(3);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFF;
+	main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Power up clock1-7 */
+	writel(0x0, &cmpll->mainpll_pwd);
+
+	/* Program the freq and divider values for clock1-7 */
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
+		&cmpll->mainpll_freq1);
+	writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
+		&cmpll->mainpll_freq2);
+	writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
+		&cmpll->mainpll_freq3);
+	writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
+		&cmpll->mainpll_freq4);
+	writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
+		&cmpll->mainpll_freq5);
+	writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
+
+	writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
+
+	writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Put the PLL in normal mode, disable bypass */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+}
+
+static void ddr_pll_bypass_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFFB;
+	ddr_pll_ctrl |= BIT(2);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+}
+
+static void ddr_pll_init_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFF7;
+	ddr_pll_ctrl |= BIT(3);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFF;
+	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	ddr_delay(10);
+
+	/* Power up clock1-5 */
+	writel(0x0, &cmpll->ddrpll_pwd);
+
+	/* Program the freq and divider values for clock1-3 */
+	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
+		&cmpll->ddrpll_freq2);
+	writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
+	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+	ddr_delay(1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+
+	ddr_delay(5);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Power up RCD */
+	writel(BIT(0), DDR_RCD);
+}
+
+static void peripheral_enable(void)
+{
+	/* Wake-up the l3_slow clock */
+	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+
+	/*
+	 * Note on Timers:
+	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+	 * Timer 0 mux should not be changed
+	 *
+	 * To access the timer registers we need the to be
+	 * enabled which is what we do in the first step
+	 */
+
+	/* Enable timer1 */
+	writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
+	/* Select timer1 clock to be CLKIN (27MHz) */
+	writel(BIT(1), CM_TIMER1_CLKSEL);
+
+	/* Wait for timer1 to be ON-ACTIVE */
+	while (((readl(&cmalwon->l3slowclkstctrl)
+					& (0x80000<<1))>>20) != 1)
+		;
+	/* Wait for timer1 to be enabled */
+	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
+		;
+	/* Active posted mode */
+	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
+	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
+		;
+	/* Start timer1  */
+	writel(BIT(0), (DM_TIMER1_BASE + 0x38));
+
+	/* eFuse */
+	writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
+	while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
+		;
+
+	/* Enable gpio0 */
+	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
+	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
+		;
+	writel((BIT(8)), &cmalwon->gpio0clkctrl);
+
+	/* Enable spi */
+	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
+	while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable i2c0 */
+	writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
+	while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable ethernet0 */
+	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+
+	/* Enable hsmmc */
+	writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
+	while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
+		;
+}
+
+void setup_clocks_for_console(void)
+{
+	/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
+	writel(0x0, CM_SYSCLK10_CLKSEL);
+
+	ddr_pll_bypass_ti816x();
+
+	/* Enable uart0-2 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
+	while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
+	while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
+		;
+	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+		;
+}
+
+void prcm_init(void)
+{
+	/* Enable the control */
+	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+	main_pll_init_ti816x();
+	ddr_pll_init_ti816x();
+
+	/*
+	 * With clk freqs setup to desired values,
+	 * enable the required peripherals
+	 */
+	peripheral_enable();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index ad7b70f93..59ad25c5b 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -35,16 +35,21 @@ void dram_init_banksize(void)
 }
 
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifdef CONFIG_TI81XX
 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
 				(struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
 static struct vtp_reg *vtpreg[2] = {
 				(struct vtp_reg *)VTP0_CTRL_ADDR,
 				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
 #ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
 
+#ifdef CONFIG_TI81XX
 void config_dmm(const struct dmm_lisa_map_regs *regs)
 {
 	enable_dmm_clocks();
@@ -59,7 +64,9 @@ void config_dmm(const struct dmm_lisa_map_regs *regs)
 	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
 	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
 }
+#endif
 
+#ifndef CONFIG_TI816X
 static void config_vtp(int nr)
 {
 	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -74,14 +81,20 @@ static void config_vtp(int nr)
 			VTP_CTRL_READY)
 		;
 }
+#endif
+
+void __weak ddr_pll_config(unsigned int ddrpll_m)
+{
+}
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
 {
-	enable_emif_clocks();
 	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
 	config_vtp(nr);
+#endif
 	config_cmd_ctrl(ctrl, nr);
 
 	config_ddr_data(data, nr);
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index f81c9a8ba..b6eb46678 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -69,9 +69,13 @@ void gpmc_init(void)
 #endif
 	/* global settings */
 	writel(0x00000008, &gpmc_cfg->sysconfig);
-	writel(0x00000100, &gpmc_cfg->irqstatus);
-	writel(0x00000100, &gpmc_cfg->irqenable);
+	writel(0x00000000, &gpmc_cfg->irqstatus);
+	writel(0x00000000, &gpmc_cfg->irqenable);
+#ifdef CONFIG_NOR
+	writel(0x00000200, &gpmc_cfg->config);
+#else
 	writel(0x00000012, &gpmc_cfg->config);
+#endif
 	/*
 	 * Disable the GPMC0 config set by ROM code
 	 */
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
index 792a828cb..b61cd69bc 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -15,7 +15,7 @@
 
 #undef SYSTIMER_BASE
 #define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
-#define SYSTIMER_RATE		150000000
+#define SYSTIMER_RATE		(150000000 / 256)
 
 static ulong timestamp;
 static ulong lastinc;
@@ -29,11 +29,11 @@ int timer_init(void)
 	/*
 	 * Setup timer0
 	 */
+	writel(0, &systimer_base->timer0control);
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
 	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
-	writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control);
-
-	reset_timer_masked();
+	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
+		&systimer_base->timer0control);
 
 	return 0;
 
@@ -113,5 +113,5 @@ ulong get_timer_masked(void)
 
 ulong get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return SYSTIMER_RATE;
 }
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 3bdb553ff..7efb0d209 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -452,6 +452,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+void enable_ipu_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+}
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 32572eea6..8150bffb8 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -16,6 +16,8 @@
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
 #include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
 
 struct scu_regs {
 	u32	ctrl;
@@ -212,3 +214,44 @@ const struct boot_mode soc_boot_modes[] = {
 void s_init(void)
 {
 }
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 98f29d466..75b375326 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -21,7 +21,7 @@ COBJS	+= vc.o
 COBJS	+= abb.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifeq ($(CONFIG_OMAP34XX),)
 COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 6b9ce369f..6b4772b68 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -40,7 +40,8 @@ void save_omap_boot_params(void)
 
 	if ((boot_device >= MMC_BOOT_DEVICES_START) &&
 	    (boot_device <= MMC_BOOT_DEVICES_END)) {
-#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX)
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \
+	!defined(CONFIG_AM43XX)
 		if ((omap_hw_init_context() ==
 				      OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
 			gd->arch.omap_boot_params.omap_bootmode =
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 20fa678f9..758059407 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -196,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params
 	return &dpll_data->ddr[sysclk_ind];
 }
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+static const struct dpll_params *get_gmac_dpll_params
+			(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	if (!dpll_data->gmac)
+		return NULL;
+	return &dpll_data->gmac[sysclk_ind];
+}
+#endif
+
 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 				u8 lock, char *dpll)
 {
@@ -398,6 +410,12 @@ static void setup_dplls(void)
 	params = get_ddr_dpll_params(*dplls_data);
 	do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
 		      params, DPLL_LOCK, "ddr");
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+	params = get_gmac_dpll_params(*dplls_data);
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
+		      DPLL_LOCK, "gmac");
+#endif
 }
 
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index ece365507..b0e1caa35 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -153,7 +153,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	 * un-locked frequency & default RL
 	 */
 	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 
 	do_ext_phy_settings(base, regs);
 
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 3acbc9c86..e903ed9ac 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -478,6 +478,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
 	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 }
 
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr = ptr + clk_index;
+
+	/* PER2 DPLL (DPLL5) */
+	sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+	sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+	sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+	sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+	sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
+	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
 {
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -582,7 +600,7 @@ void prcm_init(void)
 
 		dpll3_init_36xx(0, clk_index);
 		dpll4_init_36xx(0, clk_index);
-		dpll5_init_34xx(0, clk_index);
+		dpll5_init_36xx(0, clk_index);
 		iva_init_36xx(0, clk_index);
 		mpu_init_36xx(0, clk_index);
 
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index bdf74ea3c..98c3c03a0 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -464,6 +464,19 @@ per_36x_dpll_param:
 .word 26000,    432,   12,     9,      16,     9,     4,      3,      1
 .word 38400,    360,   15,     9,      16,     5,     4,      3,      1
 
+per2_36x_dpll_param:
+/* 12MHz */
+.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
+/* 13MHz */
+.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
+/* 19.2MHz */
+.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
+/* 26MHz */
+.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
+/* 38.4MHz */
+.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
+
+
 ENTRY(get_36x_mpu_dpll_param)
 	adr	r0, mpu_36x_dpll_param
 	mov	pc, lr
@@ -483,3 +496,8 @@ ENTRY(get_36x_per_dpll_param)
 	adr	r0, per_36x_dpll_param
 	mov	pc, lr
 ENDPROC(get_36x_per_dpll_param)
+
+ENTRY(get_36x_per2_dpll_param)
+	adr	r0, per2_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_per2_dpll_param)
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index 1832affa5..e64940965 100644
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
@@ -21,6 +21,17 @@
 struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_CMD_NAND)
+#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+	SMNAND_GPMC_CONFIG1,
+	SMNAND_GPMC_CONFIG2,
+	SMNAND_GPMC_CONFIG3,
+	SMNAND_GPMC_CONFIG4,
+	SMNAND_GPMC_CONFIG5,
+	SMNAND_GPMC_CONFIG6,
+	0,
+};
+#else
 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG1,
 	M_NAND_GPMC_CONFIG2,
@@ -29,6 +40,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG5,
 	M_NAND_GPMC_CONFIG6, 0
 };
+#endif
 #endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 9a3303f70..258786b50 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -342,9 +342,9 @@ int print_cpuinfo (void)
 	}
 
 	if (CPU_OMAP36XX == get_cpu_family())
-		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
-			cpu_family_s, cpu_s, sec_s,
-			rev_s_37xx[get_cpu_rev()], max_clk);
+		printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
+		       cpu_family_s, cpu_s, sec_s,
+		       rev_s_37xx[get_cpu_rev()], max_clk);
 	else
 		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 			cpu_family_s, cpu_s, sec_s,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ea3554d97..fbbc48662 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -247,6 +247,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 	{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
+static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
+	{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
 struct dplls omap5_dplls_es1 = {
 	.mpu = mpu_dpll_params_800mhz,
 	.core = core_dpll_params_2128mhz_ddr532,
@@ -283,6 +293,7 @@ struct dplls dra7xx_dplls = {
 	.iva = iva_dpll_params_2330mhz_dra7xx,
 	.usb = usb_dpll_params_1920mhz,
 	.ddr = ddr_dpll_params_2128mhz,
+	.gmac = gmac_dpll_params_2000mhz,
 };
 
 struct pmic_data palmas = {
@@ -382,6 +393,9 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_l3init_clkstctrl,
 		(*prcm)->cm_memif_clkstctrl,
 		(*prcm)->cm_l4cfg_clkstctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+		(*prcm)->cm_gmac_clkstctrl,
+#endif
 		0
 	};
 
@@ -409,6 +423,9 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
 		(*prcm)->cm_l4per_uart3_clkctrl,
 		(*prcm)->cm_l4per_i2c1_clkctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+		(*prcm)->cm_gmac_gmac_clkctrl,
+#endif
 		0
 	};
 
@@ -465,7 +482,6 @@ void enable_basic_uboot_clocks(void)
 		(*prcm)->cm_l3init_fsusb_clkctrl,
 		0
 	};
-
 	do_enable_clocks(clk_domains_essential,
 			 clk_modules_hw_auto_essential,
 			 clk_modules_explicit_en_essential,
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 54d8c2b68..579818d55 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -378,6 +378,10 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
+	.control_core_mac_id_0_lo		= 0x4A002514,
+	.control_core_mac_id_0_hi		= 0x4A002518,
+	.control_core_mac_id_1_lo		= 0x4A00251C,
+	.control_core_mac_id_1_hi		= 0x4A002520,
 	.control_core_mmr_lock1			= 0x4A002540,
 	.control_core_mmr_lock2			= 0x4A002544,
 	.control_core_mmr_lock3			= 0x4A002548,
@@ -798,6 +802,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_ssc_deltamstep_dpll_ddrphy		= 0x4a00522c,
 	.cm_clkmode_dpll_dsp			= 0x4a005234,
 	.cm_shadow_freq_config1			= 0x4a005260,
+	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
 
 	/* cm1.mpu */
 	.cm_mpu_mpu_clkctrl			= 0x4a005320,
@@ -895,6 +900,8 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
 	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
 	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_gmac_clkstctrl			= 0x4a0093c0,
+	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
 
 	/* cm2.l4per */