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authorMike Williams <mike@mikebwilliams.com>2011-07-22 04:01:30 +0000
committerWolfgang Denk <wd@denx.de>2011-07-28 21:27:36 +0200
commit1626308797ac4184e73e56d275a1b8da11a62d5b (patch)
treed12fd0d610303c3d2351d8ace314a643f20e0fc9 /arch/arm/cpu
parent2469c4b2dbdd601a4e44ecf9925b99bd2cd1b43f (diff)
downloadolio-uboot-2014.01-1626308797ac4184e73e56d275a1b8da11a62d5b.tar.xz
olio-uboot-2014.01-1626308797ac4184e73e56d275a1b8da11a62d5b.zip
cleanup: Fix typos and misspellings in various files.
Recieve/Receive recieve/receive Interupt/Interrupt interupt/interrupt Addres/Address addres/address Signed-off-by: Mike Williams <mike@mikebwilliams.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm720t/lpc2292/mmc_hw.c4
-rw-r--r--arch/arm/cpu/arm720t/start.S2
-rw-r--r--arch/arm/cpu/arm920t/at91/timer.c2
-rw-r--r--arch/arm/cpu/arm920t/start.S4
-rw-r--r--arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c2
-rw-r--r--arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h2
-rw-r--r--arch/arm/cpu/ixp/npe/include/IxNpeA.h2
-rw-r--r--arch/arm/cpu/ixp/npe/include/IxQMgr.h2
-rw-r--r--arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h2
-rw-r--r--arch/arm/cpu/lh7a40x/start.S2
-rw-r--r--arch/arm/cpu/sa1100/start.S2
11 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
index b4dc4a6e2..bd6a5b120 100644
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
@@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
@@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
- /* The addres on the MMC/SD-card is in bytes,
+ /* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 091b7d891..ecb92ef21 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -274,7 +274,7 @@ _dynsym_start_ofs:
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
INTMR2: .word 0x80001280 @ 16 bit size
INTMR3: .word 0x80002280 @ 8 bit size
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
index c321e2864..91607b525 100644
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -59,7 +59,7 @@ int timer_init(void)
when the value in TC_RC is reached */
writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+ writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 2a536674b..0090f894d 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -142,11 +142,11 @@ copyex:
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
index 09f69ce32..642e67ae8 100644
--- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
+++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
@@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId,
&dispatchQInfo[qId].statusMask);
- /* Set the interupt source is this queue is in the range 0-31 */
+ /* Set the interrupt source is this queue is in the range 0-31 */
if (qId < IX_QMGR_MIN_QUEUPP_QID)
{
ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
index 0ee412355..4e0de8235 100644
--- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
+++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
@@ -279,7 +279,7 @@ typedef struct
BOOL portInitialized;
UINT32 npeId; /**< NpeId for this port */
IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+ IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
} IxEthAccPortDataInfo;
extern IxEthAccPortDataInfo ixEthAccPortData[];
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
index 7427cc41c..90669c27e 100644
--- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h
+++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
@@ -717,7 +717,7 @@ typedef struct
*/
typedef struct
{
- UINT32 rxBitField; /**< Recieved bit field */
+ UINT32 rxBitField; /**< Received bit field */
UINT32 atmCellHeader; /**< ATM Cell Header */
UINT32 rsvdWord0; /**< Reserved field */
UINT16 currMbufLen; /**< Mbuf Length */
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
index 165ed96e5..03d7e0709 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
@@ -570,7 +570,7 @@ typedef enum
* @brief Queue interrupt source select.
*
* This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
* queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
* NE(Nearly Empty) status flag.
*
diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
index f7194e72e..b65d621e3 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
@@ -404,7 +404,7 @@
*
* @def IX_ETH_ACC_RX_FRAME_ETH_Q
*
-* @brief Eth0/Eth1 NPE Frame Recieve Q.
+* @brief Eth0/Eth1 NPE Frame Receive Q.
*
* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
*
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index 61bce5f18..14e985457 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -124,7 +124,7 @@ reset:
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
+#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index c3acf7aae..7223c471b 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -263,7 +263,7 @@ _dynsym_start_ofs:
*/
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 20:22:42 +0000