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| author | Tom Rini <trini@ti.com> | 2013-06-22 07:38:12 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-22 07:38:12 -0400 |
| commit | 348e47f766ac228fb02d1af562b2e9a4c69355db (patch) | |
| tree | 778ffb90bb670f45fa7a0dae78010c8128c4d84d /arch/arm/cpu/armv7/am33xx/board.c | |
| parent | 5707233880090f785c33df32c04549ea1aeef61e (diff) | |
| parent | fbf87b1823dd5ebc2a384711ea2c677543019ece (diff) | |
| download | olio-uboot-2014.01-348e47f766ac228fb02d1af562b2e9a4c69355db.tar.xz olio-uboot-2014.01-348e47f766ac228fb02d1af562b2e9a4c69355db.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/board.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/board.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 885fb2d20..b935a29a3 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -149,3 +149,43 @@ int arch_misc_init(void) #endif return 0; } + +#ifdef CONFIG_SPL_BUILD +void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +void uart_soft_reset(void) +{ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + u32 regval; + + regval = readl(&uart_base->uartsyscfg); + regval |= UART_RESET; + writel(regval, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regval = readl(&uart_base->uartsyscfg); + regval |= UART_SMART_IDLE_EN; + writel(regval, &uart_base->uartsyscfg); +} +#endif |