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| author | Wolfgang Denk <wd@denx.de> | 2011-05-18 14:31:56 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-05-18 14:31:56 +0200 |
| commit | 0ea91423f47461bf7eaed2d4aff198076dd07fd5 (patch) | |
| tree | b5201f976fe3f7f5ed6f485f7ef81d8d8c9ec033 /arch/arm/cpu/arm926ejs/at91/clock.c | |
| parent | ce6400a0f88f9648d6def519244ea8c33c7612b2 (diff) | |
| parent | 24890f11980eb70d835ca7e0b00d32284d8f546c (diff) | |
| download | olio-uboot-2014.01-0ea91423f47461bf7eaed2d4aff198076dd07fd5.tar.xz olio-uboot-2014.01-0ea91423f47461bf7eaed2d4aff198076dd07fd5.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (40 commits)
avr32: add ATAG_BOARDINFO
at91: reworked support for otc570 board
at91: reworked support for meesc board
hammerhead: move CONFIG_SYS_TEXT_BASE to header
mimc200: move CONFIG_SYS_TEXT_BASE to header
favr-32-ezkit: move CONFIG_SYS_TEXT_BASE to header
atstk100x: move CONFIG_SYS_TEXT_BASE to header
atngw100: move CONFIG_SYS_TEXT_BASE to header
mimc200: fix "#define XXXX 1"
hammerhead: fix "#define XXXX 1"
favr-32-ezkit: fix "#define XXXX 1"
atstk1006: fix "#define XXXX 1"
atstk1004: fix "#define XXXX 1"
atstk1003: fix "#define XXXX 1"
atstk1002: fix "#define XXXX 1"
atngw100: fix "#define XXXX 1"
avr32: use single linker script
avr32/config.mk: simplify PLATFORM_RELFLAGS
avr32: fix linking
Add support for Bluewater Systems Snapper 9260 and 9G20 modules
...
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91/clock.c')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/at91/clock.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 7a10a7787..608af2cf7 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -12,8 +12,8 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> @@ -57,7 +57,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return AT91_SLOW_CLOCK; + return CONFIG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -145,7 +145,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; #ifndef CONFIG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* @@ -159,7 +159,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->main_clk_rate_hz = main_clock; |