Merge git://git.denx.de/u-boot

1 files changed, 1 insertions, 184 deletions

diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 2f914e9b4..c2a7763ff 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -43,11 +43,7 @@ _start: b	reset
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
-#ifdef CONFIG_LPC2292
-	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
 	ldr	pc, _not_used
-#endif
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
@@ -151,10 +147,6 @@ reset:
 	bl	cpu_init_crit
 #endif
 
-#ifdef CONFIG_LPC2292
-	bl	lowlevel_init
-#endif
-
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -291,148 +283,9 @@ _dynsym_start_ofs:
  *************************************************************************
  */
 
-#if defined(CONFIG_LPC2292)
-PLLCFG_ADR:	.word	PLLCFG
-PLLFEED_ADR:	.word	PLLFEED
-PLLCON_ADR:	.word	PLLCON
-PLLSTAT_ADR:	.word	PLLSTAT
-VPBDIV_ADR:	.word	VPBDIV
-MEMMAP_ADR:	.word	MEMMAP
-
-#endif
-
 cpu_init_crit:
-#if defined(CONFIG_NETARM)
-	/*
-	 * prior to software reset : need to set pin PORTC4 to be *HRESET
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-			NETARM_GEN_PORT_DIR(0x10))
-	str	r1, [r0, #+NETARM_GEN_PORTC]
-	/*
-	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-	 *		    for an explanation of this process
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	/*
-	 * setup PLL and System Config
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-
-	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
-			NETARM_GEN_SYS_CFG_BUSFULL | \
-			NETARM_GEN_SYS_CFG_USER_EN | \
-			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-			NETARM_GEN_SYS_CFG_BUSARB_INT | \
-			NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-			NETARM_GEN_PLL_CTL_POLTST_DEF | \
-			NETARM_GEN_PLL_CTL_INDIV(1) | \
-			NETARM_GEN_PLL_CTL_ICP_DEF | \
-			NETARM_GEN_PLL_CTL_OUTDIV(2) )
-	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
 
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	mov	r1, #0
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
-
-	/*
-	 * Mask off all IRQ sources
-	 */
-	ldr	r1, =REG_INTMASK
-	ldr	r0, =0x3FFFFF
-	str	r0, [r1]
-
-	/*
-	 * Disable Cache
-	 */
-	ldr r0, =REG_SYSCFG
-	ldr r1, =0x83ffffa0	/* cache-disabled  */
-	str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	/* Set-up PLL */
-	mov	r3, #0xAA
-	mov	r4, #0x55
-	/* First disconnect and disable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x00
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set new M and P values */
-	ldr	r0, PLLCFG_ADR
-	mov	r1, #0x23	/* M=4 and P=2 */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Then enable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x01	/* PLL enable bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Wait for the lock */
-	ldr	r0, PLLSTAT_ADR
-	mov	r1, #0x400	/* lock bit */
-lock_loop:
-	ldr	r2, [r0]
-	and	r2, r1, r2
-	cmp	r2, #0
-	beq	lock_loop
-	/* And finally connect the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x03	/* PLL enable bit and connect bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set-up VPBDIV register */
-	ldr	r0, VPBDIV_ADR
-	mov	r1, #0x01	/* VPB clock is same as process clock */
-	str	r1, [r0]
-#elif defined(CONFIG_TEGRA)
-	/* No cpu_init_crit for tegra as yet */
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-	/* set clock speed */
-	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-	/* !!! not doing DRAM refresh properly! */
-	ldr	r0, SYSCON3
-	ldr	r1, [r0]
-	bic	r1, r1, #CLKCTL
-	orr	r1, r1, #CLKCTL_36
-	str	r1, [r0]
-#endif
-
-#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
+#if !defined(CONFIG_TEGRA)
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -610,39 +463,3 @@ fiq:
 
 #endif
 #endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_NETARM)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =NETARM_MEM_MODULE_BASE
-	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-	ldr	r1, =0xFFFFF000
-	and	r0, r1, r0
-	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-	add	r0, r1, r0
-	ldr	r4, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	mov	pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov	pc, r0
-#elif defined(CONFIG_TEGRA)
-	/* No specific reset actions for tegra as yet */
-#else
-#error No reset_cpu() defined for current CPU type
-#endif