Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  ARM926EJS: Fix cache.c to comply with checkpatch.pl
  ARM926EJS: Make asm routines volatile in cache ops
  MX35: mx35pdk: wrong board revision
  ARM1136: MX35: Make asm routines volatile in cache ops
  ARM: add u-boot.imx as target for i.MX SOCs
  M28: Pull out CONFIG_APBH_DMA so it's always enabled
  DMA: Split the APBH DMA init into block and channel init
  imx: Return gpio_set_value in gpio_direction_output
  imx: Use GPIO_TO_PORT macro in the gpio driver instead of (gpio >> 5)
  imx: Add GPIO_TO_PORT macro in the mxc_gpio driver
  imx: Remove unneeded/repititive definitions from imx headers
  i.MX28: Allow coexistence of PIO and DMA mode for SD/MMC
  MX31: mx31pdk: drop enable_caches from board file
  i.MX28: Fix initial stack pointer position
  mx35: mx35pdk: fix when cache functions are linked
  mx35: flea3: fix when cache functions are linked
  ARM: 926ejs: use debug() for misaligned addresses
  ARM1136: add cache flush and invalidate operations
  mx6qsabrelite: Fix the serial console port
  mx6qsabrelite: Add boot switch setting information into the README
  i.MX6: mx6qsabrelite: add cache commands if cache is enabled
  i.MX6: implement enable_caches()
  i.MX6: define CACHELINE_SIZE
  MX53: DDR: Fix ZQHWCTRL field TZQ_CS
  mx28evk: Add a README file
  mx28: Split the README into a common part and a m28 specific part
  tricorder: Load kernel from ubifs
  tricorder: Add UBIFS
  cm-t35: fix Ethernet reset timing
  hawkboard: Add CONFIG_SPL_LIBGENERIC_SUPPORT
  BeagleBoard: Remove userbutton command and use gpio command instead
  OMAP: Move omap1510inn to Unmaintained / Orphaned

1 files changed, 100 insertions, 3 deletions

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index 2b9163173..f72bab669 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -70,8 +70,105 @@ int cleanup_before_linux (void)
 static void cache_flush(void)
 {
 	unsigned long i = 0;
+	/* clean entire data cache */
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+	/* invalidate both caches and flush btb */
+	asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+	/* mem barrier to sync things */
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
+
+void invalidate_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static inline int bad_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
 
-	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (bad_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (bad_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
 }
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */