diff options
| author | Evan Wilson <evan@oliodevices.com> | 2014-10-15 18:20:17 +0000 |
|---|---|---|
| committer | Gerrit Code Review <gerrit2@ip-172-31-25-77.us-west-1.compute.internal> | 2014-10-09 19:34:20 +0000 |
| commit | cb5da424e7738bcf6c25febceee07700338faa44 (patch) | |
| tree | a345971ee4f7de9cf0a3213e2a7cb2aae02f24bb | |
| parent | 95a5724b19c0c1281a7f72ad1812079a53a52dbc (diff) | |
| parent | a7b80a0b2349dc08bb49a601a444330a08a23469 (diff) | |
| download | olio-uboot-2014.01-cb5da424e7738bcf6c25febceee07700338faa44.tar.xz olio-uboot-2014.01-cb5da424e7738bcf6c25febceee07700338faa44.zip | |
Merge "OMAP3H1: Pinmux: New pinmux for Bluetooth to work Set BCM 20702 REG_EN and WAKE as GPIOs Putting Bluetooth SPI-SOMI into safe mode (pulled up), so that Bluetooth chip doesn't enter SPI mode" into H1-2014.01
| -rw-r--r-- | board/olio/h1/pinmux.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h index 5bba7c772..3cdf5a3d1 100644 --- a/board/olio/h1/pinmux.h +++ b/board/olio/h1/pinmux.h @@ -77,7 +77,7 @@ MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IEN | PD | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IEN | PD | M7 )) /* safe_mode */\
-MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PI | M4 )) /* gpio_93 */\
MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IEN | PU | M7 )) /* safe_mode */\
@@ -199,12 +199,12 @@ MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PU | M7 )) /* safe_mode */\ MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PD | M7 )) /* safe_mode */\
-MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PU | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PD | M7 )) /* safe_mode */\
-MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IDIS | PI | M4 )) /* gpio_180 */\
MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PD | M7 )) /* safe_mode */\
|