diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-01-19 10:52:04 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-19 22:58:24 -0600 |
| commit | b7070904327d10eb789ccafa4622659ffaa6645c (patch) | |
| tree | 93bf0da1af37e218c1e73eeb81e3191f519c5653 | |
| parent | 768d5b2bafd702c711d79b67ad0a289d22938c40 (diff) | |
| download | olio-uboot-2014.01-b7070904327d10eb789ccafa4622659ffaa6645c.tar.xz olio-uboot-2014.01-b7070904327d10eb789ccafa4622659ffaa6645c.zip | |
ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDB
u-boot cannot be compiled after disabling CONFIG_PCI.
Place PCI related codes under #ifdef CONFIG_PCI
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | board/freescale/p1_p2_rdb/p1_p2_rdb.c | 4 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 4 | ||||
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 13 |
3 files changed, 14 insertions, 7 deletions
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 440fcb924..078094200 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -222,7 +222,9 @@ void ft_board_setup(void *blob, bd_t *bd) base = getenv_bootm_low(); size = getenv_bootm_size(); +#if defined(CONFIG_PCI) ft_pci_board_setup(blob); +#endif /* #if defined(CONFIG_PCI) */ fdt_fixup_memory(blob, (u64)base, (u64)size); } diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 93d0bf7bc..b85c268db 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), +#if defined(CONFIG_PCI) /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -68,6 +69,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), +#endif /* #if defined(CONFIG_PCI) */ /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index d18d2f6fb..bf3474004 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -83,17 +83,23 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif /* #if defined(CONFIG_PCI) */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_PCI) #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ +#endif + #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -364,6 +370,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#if defined(CONFIG_PCI) #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -385,8 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 @@ -405,11 +410,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 -#endif +#if defined(CONFIG_TSEC_ENET) #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 |