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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-12-12 12:09:01 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-02 14:10:13 -0800 |
| commit | 562de1d6da5bdc1789bd258d464d6ca57571861d (patch) | |
| tree | 84ada120ab90055522b69a080817f2c5bbb13bc4 | |
| parent | fbe76ae4e3bacd5183294488947ec148df28d55b (diff) | |
| download | olio-uboot-2014.01-562de1d6da5bdc1789bd258d464d6ca57571861d.tar.xz olio-uboot-2014.01-562de1d6da5bdc1789bd258d464d6ca57571861d.zip | |
board/t1040qds: Relax IFC FPGA timings
Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.
So, Increase TCH as 0x8 i.e. 8 ip_clk.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| -rw-r--r-- | include/configs/T1040QDS.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index d0ebd6aba..8ecf188bd 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -248,7 +248,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 |