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| author | Heiko Schocher <hs@denx.de> | 2009-02-11 19:26:15 +0100 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-02-16 19:17:19 -0600 |
| commit | 2b68b23373f96199a0cafbfd7a9f79ed62381ebb (patch) | |
| tree | 08fe730da567918dc7400403de7e777ad60348d6 | |
| parent | c9e34fe2e86f7b6cc8260f4b24cbdc7dd81e04c5 (diff) | |
| download | olio-uboot-2014.01-2b68b23373f96199a0cafbfd7a9f79ed62381ebb.tar.xz olio-uboot-2014.01-2b68b23373f96199a0cafbfd7a9f79ed62381ebb.zip | |
83xx: add missing TIMING_CFG1_CASLAT_* defines
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | include/mpc83xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 3554fdd4e..fab37516c 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -890,6 +890,8 @@ #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ +#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ +#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ |