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| author | trem <tremyfr@yahoo.fr> | 2013-09-06 17:33:45 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-09-10 19:12:55 +0200 |
| commit | e24278aff2684ae459353c44fa7ee91c04e67413 (patch) | |
| tree | 52e7f4f528eeb9abfc96af2570b4060651da7116 | |
| parent | d9b8946035e8cdd237404f3b83d6caf21f84ce73 (diff) | |
| download | olio-uboot-2014.01-e24278aff2684ae459353c44fa7ee91c04e67413.tar.xz olio-uboot-2014.01-e24278aff2684ae459353c44fa7ee91c04e67413.zip | |
mx27: add missing constant for mx27
Add some missing constant (chip select, ...)
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Acked-by: Stefano Babic <sbabic@denx.de>
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx27/imx-regs.h | 6 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c index 8db2a67f3..629b72774 100644 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c @@ -38,5 +38,10 @@ int main(void) DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); + return 0; } diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index a27145ba2..92c847e44 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -169,7 +169,7 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; - } bank[1]; + } bank[2]; }; struct fuse_bank0_regs { @@ -209,9 +209,13 @@ struct fuse_bank0_regs { #define IIM_BASE_ADDR IMX_IIM_BASE #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) +#define IMX_NFC_BASE (0xD8000000) #define IMX_ESD_BASE (0xD8001000) #define IMX_WEIM_BASE (0xD8002000) +#define NFC_BASE_ADDR IMX_NFC_BASE + + /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) #define UART4_RTS_CTL (1 << 24) |