diff options
| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2011-03-03 09:18:56 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-07 08:49:28 -0600 |
| commit | b71ea33699bb694964929e2cdced80ef794bde69 (patch) | |
| tree | aadaa4c2e5edd0b040c629286fdf16636c736f9d | |
| parent | 509e19cab43ba38311749eba5ceebd806116ce38 (diff) | |
| download | olio-uboot-2014.01-b71ea33699bb694964929e2cdced80ef794bde69.tar.xz olio-uboot-2014.01-b71ea33699bb694964929e2cdced80ef794bde69.zip | |
fsl_esdhc: Correcting esdhc timeout counter calculation
- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f3cccbe9b..0962ac447 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -210,7 +210,21 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ - timeout = fls(mmc->tran_speed/10) - 1; + /* + * 1)Timeout period = (2^(timeout+13)) SD Clock cycles + * 2)Timeout period should be minimum 0.250sec as per SD Card spec + * So, Number of SD Clock cycles for 0.25sec should be minimum + * (SD Clock/sec * 0.25 sec) SD Clock cycles + * = (mmc->tran_speed * 1/4) SD Clock cycles + * As 1) >= 2) + * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * Taking log2 both the sides + * => timeout + 13 >= log2(mmc->tran_speed/4) + * Rounding up to next power of 2 + * => timeout + 13 = log2(mmc->tran_speed/4) + 1 + * => timeout + 13 = fls(mmc->tran_speed/4) + */ + timeout = fls(mmc->tran_speed/4); timeout -= 13; if (timeout > 14) |