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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2012-05-31 07:23:57 +0000 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2012-07-10 11:35:38 +0200 |
| commit | 913db79427ba6fc71a179a6faff96756ebf40980 (patch) | |
| tree | 9a2041d89b2bf279ff84761ff421a5401843b6e3 | |
| parent | 695af9abc660c674966f02b0ecc85f5524a7aede (diff) | |
| download | olio-uboot-2014.01-913db79427ba6fc71a179a6faff96756ebf40980.tar.xz olio-uboot-2014.01-913db79427ba6fc71a179a6faff96756ebf40980.zip | |
ipu_common: Only apply the erratum to MX51
The following erratum :
"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"
only applies to mx51, so restrict its usage for this SoC only.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| -rw-r--r-- | drivers/video/ipu_common.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 9d20c864b..4caad4f12 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -401,6 +401,7 @@ void ipu_reset(void) int ipu_probe(void) { unsigned long ipu_base; +#if defined CONFIG_MX51 u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; @@ -414,6 +415,7 @@ int ipu_probe(void) temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); +#endif ipu_base = IPU_CTRL_BASE_ADDR; ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); |