Merge with /home/raj/git/u-boot

5 files changed, 25 insertions, 36 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 596e89405..67824926e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix PCI-Express on PPC440SPe rev. A.
+
 * Fix preboot message on TQM85xx after switching to hush parser.
 
 * Adapt TQM85xx ramdisk address to Linux kernel memory map
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index 5a3dd0e2b..c9eca686b 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -105,17 +105,14 @@ tlbtabA:
 	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_4K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_4K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE, SZ_4K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-
-	tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
 
 /**************************************************************************
@@ -152,8 +149,4 @@ tlbtabB:
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-
-	tlbentry(CFG_PCIE1_REGBASE, SZ_1K, 0x60000400, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE3_REGBASE, SZ_1K, 0x60001400, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE5_REGBASE, SZ_1K, 0x60002400, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index a6589ec26..af12839c2 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -1032,6 +1032,7 @@ void pcie_setup_hoses(void)
 			continue;
 
 		yucca_setup_pcie_fpga_rootpoint(i);
+
 		if (ppc440spe_init_pcie_rootport(i)) {
 			printf("PCIE%d: initialization failed\n", i);
 			continue;
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index cbc93dd02..2e920aadf 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) {
 	 */
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400);
-		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01);
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
-		utl_base = (unsigned int *)(CFG_PCIE1_REGBASE);
 		break;
 
 	case 1:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400);
-		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01);
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
-		utl_base = (unsigned int *)(CFG_PCIE3_REGBASE);
 		break;
 
 	case 2:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400);
-		mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01);
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
-		utl_base = (unsigned int *)(CFG_PCIE5_REGBASE);
 		break;
 	}
-
+	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+	
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
 	 */
@@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
 	out_be32(utl_base + PEUTL_IPHBSZ,  0x08000000);
 	out_be32(utl_base + PEUTL_IPDBSZ,  0x10000000);
 	out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
-	out_be32(utl_base + PEUTL_PCTL,    0x8080007d);
+	out_be32(utl_base + PEUTL_PCTL,    0x80800066);
 }
 
 static int check_error(void)
@@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
 	 *     PCIE1: 0xd_2000_0000
 	 *     PCIE2: 0xd_4000_0000
 	 */
+
 	switch (port) {
 	case 0:
 		if (ppc440spe_revB()) {
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 9dd9e5eae..26a330eea 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -67,8 +67,9 @@
 #define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
 #define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
 
-#define CFG_PCIE_MEMBASE	0xB0000000	/* mapped PCIe memory	*/
+#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
 #define CFG_PCIE_MEMSIZE	0x01000000
+#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 
 #define CFG_PCIE0_CFGBASE	0xc0000000
 #define CFG_PCIE0_XCFGBASE	0xc0000400
@@ -77,13 +78,6 @@
 #define CFG_PCIE2_CFGBASE	0xc0002000
 #define CFG_PCIE2_XCFGBASE	0xc0002400
 
-#define CFG_PCIE0_REGBASE	0xc0003000
-#define CFG_PCIE1_REGBASE	0xc0003400
-#define CFG_PCIE2_REGBASE	0xc0004000
-#define CFG_PCIE3_REGBASE	0xc0004400
-#define CFG_PCIE4_REGBASE	0xc0005000
-#define CFG_PCIE5_REGBASE	0xc0005400
-
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE