powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641

The MPC8641 boards actually only have PCIE not PCI.  Rename so we are
uniform with regards to names so we can replace this code with templated
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

6 files changed, 135 insertions, 137 deletions

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index bd357b866..8c8ce9585 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -32,14 +32,14 @@
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0x8000_0000     0x9fff_ffff     PCIE1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIE2 MEM                512M
  * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
  * endif
  * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
- * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
+ * 0xffc0_0000     0xffc0_ffff     PCIE1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCIE2 IO                 64K
  * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
  * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
  * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
@@ -54,10 +54,10 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
 #ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 9e881024f..a88be5a0d 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2006, 2007 Freescale Semiconductor.
+ * Copyright 2006, 2007, 2010 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -129,21 +129,21 @@ fixed_sdram(void)
 
 
 #if defined(CONFIG_PCI)
-static struct pci_controller pci1_hose;
+static struct pci_controller pcie1_hose;
 #endif /* CONFIG_PCI */
 
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif	/* CONFIG_PCI2 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif	/* CONFIG_PCIE2 */
 
 int first_free_busno = 0;
 
 void pci_init_board(void)
 {
-#ifdef CONFIG_PCI1
+#ifdef CONFIG_PCIE1
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
+	struct pci_controller *hose = &pcie1_hose;
 	struct pci_region *r = hose->regions;
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -169,16 +169,16 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BUS,
-			       CONFIG_SYS_PCI1_MEM_PHYS,
-			       CONFIG_SYS_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BUS,
-			       CONFIG_SYS_PCI1_IO_PHYS,
-			       CONFIG_SYS_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BUS,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = r - hose->regions;
@@ -195,8 +195,8 @@ void pci_init_board(void)
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
-		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
-				       + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
+		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 
 	} else {
 		puts("PCI-EXPRESS 1: Disabled\n");
@@ -204,26 +204,26 @@ void pci_init_board(void)
 }
 #else
 	puts("PCI-EXPRESS1: Disabled\n");
-#endif /* CONFIG_PCI1 */
+#endif /* CONFIG_PCIE1 */
 
-#ifdef CONFIG_PCI2
+#ifdef CONFIG_PCIE2
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	struct pci_controller *hose = &pci2_hose;
+	struct pci_controller *hose = &pcie2_hose;
 	struct pci_region *r = hose->regions;
 
 	/* outbound memory */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_MEM_BUS,
-		       CONFIG_SYS_PCI2_MEM_PHYS,
-		       CONFIG_SYS_PCI2_MEM_SIZE,
+		       CONFIG_SYS_PCIE2_MEM_BUS,
+		       CONFIG_SYS_PCIE2_MEM_PHYS,
+		       CONFIG_SYS_PCIE2_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* outbound io */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_IO_BUS,
-		       CONFIG_SYS_PCI2_IO_PHYS,
-		       CONFIG_SYS_PCI2_IO_SIZE,
+		       CONFIG_SYS_PCIE2_IO_BUS,
+		       CONFIG_SYS_PCIE2_IO_PHYS,
+		       CONFIG_SYS_PCIE2_IO_SIZE,
 		       PCI_REGION_IO);
 
 	hose->region_count = r - hose->regions;
@@ -238,7 +238,7 @@ void pci_init_board(void)
 }
 #else
 	puts("PCI-EXPRESS 2: Disabled\n");
-#endif /* CONFIG_PCI2 */
+#endif /* CONFIG_PCIE2 */
 
 }
 
@@ -253,11 +253,11 @@ ft_board_setup(void *blob, bd_t *bd)
 
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
 #endif
-#ifdef CONFIG_PCI2
-	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 #endif
 
 	/*
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index d20fa51c3..705e1c296 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -32,11 +32,11 @@
  *
  * 0x0000_0000	DDR			256M
  * 0x1000_0000	DDR2			256M
- * 0x8000_0000	PCI1 MEM		512M
- * 0xa000_0000	PCI2 MEM		512M
+ * 0x8000_0000	PCIE1 MEM		512M
+ * 0xa000_0000	PCIE2 MEM		512M
  * 0xc000_0000	RapidIO			512M
- * 0xe200_0000	PCI1 IO			16M
- * 0xe300_0000	PCI2 IO			16M
+ * 0xe200_0000	PCIE1 IO		16M
+ * 0xe300_0000	PCIE2 IO		16M
  * 0xf800_0000	CCSRBAR			2M
  * 0xfe00_0000	FLASH (boot bank)	32M
  *
@@ -49,11 +49,11 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
 #endif
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 1060f3883..b1dda1082 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -191,16 +191,16 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = {
 };
 #endif
 
-static struct pci_controller pci1_hose = {
+static struct pci_controller pcie1_hose = {
 #ifndef CONFIG_PCI_PNP
 	config_table:pci_mpc86xxcts_config_table
 #endif
 };
 #endif /* CONFIG_PCI */
 
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif	/* CONFIG_PCI2 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif	/* CONFIG_PCIE2 */
 
 int first_free_busno = 0;
 
@@ -212,10 +212,10 @@ void pci_init_board(void)
 	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 
-#ifdef CONFIG_PCI1
+#ifdef CONFIG_PCIE1
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
+	struct pci_controller *hose = &pcie1_hose;
 	struct pci_region *r = hose->regions;
 #ifdef DEBUG
 	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
@@ -236,16 +236,16 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BUS,
-			       CONFIG_SYS_PCI1_MEM_PHYS,
-			       CONFIG_SYS_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BUS,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BUS,
-			       CONFIG_SYS_PCI1_IO_PHYS,
-			       CONFIG_SYS_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BUS,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = r - hose->regions;
@@ -264,26 +264,26 @@ void pci_init_board(void)
 }
 #else
 	puts("PCI-EXPRESS1: Disabled\n");
-#endif /* CONFIG_PCI1 */
+#endif /* CONFIG_PCIE1 */
 
-#ifdef CONFIG_PCI2
+#ifdef CONFIG_PCIE2
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	struct pci_controller *hose = &pci2_hose;
+	struct pci_controller *hose = &pcie2_hose;
 	struct pci_region *r = hose->regions;
 
 	/* outbound memory */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_MEM_BUS,
-		       CONFIG_SYS_PCI2_MEM_PHYS,
-		       CONFIG_SYS_PCI2_MEM_SIZE,
+		       CONFIG_SYS_PCIE2_MEM_BUS,
+		       CONFIG_SYS_PCIE2_MEM_PHYS,
+		       CONFIG_SYS_PCIE2_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* outbound io */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_IO_BUS,
-		       CONFIG_SYS_PCI2_IO_PHYS,
-		       CONFIG_SYS_PCI2_IO_SIZE,
+		       CONFIG_SYS_PCIE2_IO_BUS,
+		       CONFIG_SYS_PCIE2_IO_PHYS,
+		       CONFIG_SYS_PCIE2_IO_SIZE,
 		       PCI_REGION_IO);
 
 	hose->region_count = r - hose->regions;
@@ -298,7 +298,7 @@ void pci_init_board(void)
 }
 #else
 	puts("PCI-EXPRESS 2: Disabled\n");
-#endif /* CONFIG_PCI2 */
+#endif /* CONFIG_PCIE2 */
 
 }
 
@@ -308,11 +308,11 @@ void ft_board_setup (void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
 #endif
-#ifdef CONFIG_PCI2
-	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 #endif
 }
 #endif
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index b183e027e..0d1f7799c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2006 Freescale Semiconductor.
+ * Copyright 2006, 2010 Freescale Semiconductor.
  *
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
@@ -58,8 +58,8 @@
 
 #ifndef CONFIG_RIO			/* RIO/PCI are mutually exclusive */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
-#define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
-#define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #endif
@@ -325,43 +325,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Addresses are mapped 1-1.
  */
 
-#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0x0000000c00000000ULL
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x0000000c00000000ULL
 #else
-#define CONFIG_SYS_PCI1_MEM_BUS		CONFIG_SYS_PCI1_MEM_VIRT
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_VIRT
 #endif
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCI1_IO_PHYS	(CONFIG_SYS_PCI1_IO_VIRT \
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_PHYS	(CONFIG_SYS_PCIE1_IO_VIRT \
 				 | CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64K */
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
 
 #ifdef CONFIG_PHYS_64BIT
 /*
- * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
+ * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
  * This will increase the amount of PCI address space available for
  * for mapping RAM.
  */
-#define CONFIG_SYS_PCI2_MEM_BUS		CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
 #else
-#define CONFIG_SYS_PCI2_MEM_BUS		(CONFIG_SYS_PCI1_MEM_BUS \
-					 + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
 #endif
-#define CONFIG_SYS_PCI2_MEM_VIRT 	(CONFIG_SYS_PCI1_MEM_VIRT \
-					 + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS	(CONFIG_SYS_PCI1_MEM_PHYS \
-					 + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
-				 + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_PHYS	(CONFIG_SYS_PCI1_IO_PHYS \
-				 + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE	CONFIG_SYS_PCI1_IO_SIZE
+#define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
 
 #if defined(CONFIG_PCI)
 
@@ -390,10 +390,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCI2_IO_VIRT
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -406,7 +406,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -422,8 +422,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
 #endif
 
-#define CONFIG_MPC86XX_PCI2
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -494,17 +492,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /* if CONFIG_PCI:
- * BAT2		PCI1 and PCI1 MEM
+ * BAT2		PCIE1 and PCIE1 MEM
  * if CONFIG_RIO
  * BAT2		Rapidio Memory
  */
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
 				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
@@ -553,14 +551,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 /*
- * BAT4		PCI1_IO and PCI2_IO
+ * BAT4		PCIE1_IO and PCIE2_IO
  */
-#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
 				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 6662bbe0e..618513ab6 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -56,8 +56,8 @@
 #define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
 #define CONFIG_PCI		1	/* Enable PCIE */
-#define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCI2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
@@ -304,23 +304,23 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS	0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_VIRT	CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_VIRT	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0xe2000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_VIRT	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000	/* 16M */
 
-#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_VIRT	CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BUS	0xe3000000
-#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_VIRT	CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_VIRT	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0xe3000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_VIRT	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
 
@@ -406,10 +406,10 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /*
@@ -449,10 +449,10 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*