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| author | Stefan Roese <sr@denx.de> | 2008-01-30 14:48:28 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-02-04 11:47:40 +0100 |
| commit | 28d77d968bfe0316deb5bf15c17f57d5ff2c8821 (patch) | |
| tree | 3abcd5c43ace3bdfcdedff146fb123c77147a4b0 | |
| parent | 2c5260f711168d5ee91c70ddbb7d897013eefc46 (diff) | |
| download | olio-uboot-2014.01-28d77d968bfe0316deb5bf15c17f57d5ff2c8821.tar.xz olio-uboot-2014.01-28d77d968bfe0316deb5bf15c17f57d5ff2c8821.zip | |
ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | cpu/ppc4xx/start.S | 4 | ||||
| -rw-r--r-- | include/configs/pcs440ep.h | 2 | ||||
| -rw-r--r-- | include/configs/yosemite.h | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 77c2aa411..06380248c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -110,6 +110,10 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ +#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! +#endif + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index d66f4bd44..07fc23e5e 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -66,7 +66,7 @@ *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) +#define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index a8eeff989..4c86bc53c 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -75,7 +75,7 @@ *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) +#define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |