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| author | Stefan Roese <sr@denx.de> | 2009-10-19 14:10:50 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-23 16:04:54 +0200 |
| commit | 23c51a2d6393cd3be9eb62cb42d92138ff6db8a9 (patch) | |
| tree | 486307272da6fce68d6d1c83569cb228288345c3 | |
| parent | 08c6a2628478ace808b3767db17e4148cac5a7fb (diff) | |
| download | olio-uboot-2014.01-23c51a2d6393cd3be9eb62cb42d92138ff6db8a9.tar.xz olio-uboot-2014.01-23c51a2d6393cd3be9eb62cb42d92138ff6db8a9.zip | |
ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clock
This patch now uses the 440EP(x)/GR(x) function to check and dynamically
reconfigure the PCI sync clock.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index d42c80253..00f640872 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -40,6 +40,15 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); +static inline u32 get_async_pci_freq(void) +{ + if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & + CONFIG_SYS_BCSR5_PCI66EN) + return 66666666; + else + return 33333333; +} + int board_early_init_f(void) { u32 sdr0_cust0; @@ -76,6 +85,9 @@ int board_early_init_f(void) mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ + /* Check and reconfigure the PCI sync clock if necessary */ + ppc4xx_pci_sync_clock_config(get_async_pci_freq()); + /* 50MHz tmrclk */ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); @@ -319,7 +331,7 @@ int checkboard(void) { char *s = getenv("serial#"); u8 rev; - u8 val; + u32 clock = get_async_pci_freq(); #ifdef CONFIG_440EPX printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); @@ -328,8 +340,7 @@ int checkboard(void) #endif rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); if (s != NULL) { puts(", serial# "); @@ -337,6 +348,15 @@ int checkboard(void) } putc('\n'); + /* + * Reconfiguration of the PCI sync clock is already done, + * now check again if everything is in range: + */ + if (ppc4xx_pci_sync_clock_config(clock)) { + printf("ERROR: PCI clocking incorrect (async=%d " + "sync=%ld)!\n", clock, get_PCI_freq()); + } + return (0); } |