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| author | Dirk Eibach <eibach@gdsys.de> | 2012-01-02 11:02:46 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2012-01-09 09:19:47 +0100 |
| commit | 06b174124e3668be9a01c943b5e0c04c9e9fd1c4 (patch) | |
| tree | d4b4dec3ae1f75df9f726fdb6c1c0e02d8feaac4 | |
| parent | 9a420986cccc9bd2c37affd931d627b3c3e72952 (diff) | |
| download | olio-uboot-2014.01-06b174124e3668be9a01c943b5e0c04c9e9fd1c4.tar.xz olio-uboot-2014.01-06b174124e3668be9a01c943b5e0c04c9e9fd1c4.zip | |
ppc4xx: Setup HICB on Io64
The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/gdsys/405ex/io64.c | 16 | ||||
| -rw-r--r-- | include/gdsys_fpga.h | 5 |
2 files changed, 20 insertions, 1 deletions
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index a997571f0..177141dcc 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -249,6 +249,7 @@ int last_stage_init(void) char str_serdes[] = "Start SERDES blocks"; char str_channels[] = "Start FPGA channels"; char str_locks[] = "Verify SERDES locks"; + char str_hicb[] = "Verify HICB status"; char str_status[] = "Verify PHY status -"; char slash[] = "\\|/-\\|/-"; @@ -312,6 +313,21 @@ int last_stage_init(void) } blank_string(strlen(str_locks)); + /* verify hicb_status */ + puts(str_hicb); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; + for (k = 0; k < 32; ++k) { + u16 status = in_le16(ch0_hicb_status_int + 4*k); + if (status) + printf("fpga %d hicb %d: hicb status %04x\n", + fpga, k, status); + /* reset events */ + out_le16(ch0_hicb_status_int + 4*k, status); + } + } + blank_string(strlen(str_hicb)); + /* verify phy status */ puts(str_status); for (k = 0; k < 32; ++k) { diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e7a072bbe..949864c0f 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -82,7 +82,10 @@ typedef struct ihs_fpga { u16 reserved_1[502]; /* 0x0014 */ u16 ch0_status_int; /* 0x0400 */ u16 ch0_config_int; /* 0x0402 */ - u16 reserved_2[7677]; /* 0x0404 */ + u16 reserved_2[126]; /* 0x0404 */ + u16 ch0_hicb_status_int;/* 0x0500 */ + u16 ch0_hicb_config_int;/* 0x0502 */ + u16 reserved_3[7549]; /* 0x0504 */ u16 reflection_high; /* 0x3ffe */ } ihs_fpga_t; #endif |