From 59fb659b065f52fcc2deed293cfbfc58f890376c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 15:30:55 -0700 Subject: OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific files In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras for comments on this patch. Signed-off-by: Paul Walmsley Cc: Jarkko Nikula Cc: Peter Ujfalusi Cc: Liam Girdwood Cc: Omar Ramirez Luna Acked-by: Omar Ramirez Luna Cc: Felipe Contreras Acked-by: Felipe Contreras Cc: Greg Kroah-Hartman Acked-by: Mark Brown Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Tested-by: Rajendra Nayak Tested-by: Santosh Shilimkar --- arch/arm/mach-omap2/pm-debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a8afb610c7d..1f5d68beabf 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -33,8 +33,8 @@ #include #include -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "pm.h" int omap2_pm_debug; -- cgit v1.2.3-70-g09d2 From c4d7e58fb52c632d8e33cd23a4917d7a7f8302ac Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:14 -0700 Subject: OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_" Now that OMAP4-specific PRCM functions have been added, distinguish the existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_". This patch should not result in any functional change. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Jarkko Nikula Cc: Peter Ujfalusi Cc: Liam Girdwood Cc: Mark Brown Tested-by: Santosh Shilimkar Tested-by: Rajendra Nayak --- arch/arm/mach-omap2/clkt2xxx_apll.c | 10 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 8 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 12 +- arch/arm/mach-omap2/clockdomain.c | 22 +- arch/arm/mach-omap2/cm2xxx_3xxx.c | 352 ++++++++++++++------------- arch/arm/mach-omap2/cm2xxx_3xxx.h | 10 +- arch/arm/mach-omap2/control.c | 40 +-- arch/arm/mach-omap2/dsp.c | 12 +- arch/arm/mach-omap2/pm-debug.c | 8 +- arch/arm/mach-omap2/pm24xx.c | 194 +++++++-------- arch/arm/mach-omap2/pm34xx.c | 143 +++++------ arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 66 ++--- arch/arm/mach-omap2/powerdomain44xx.c | 33 +-- arch/arm/mach-omap2/prcm.c | 16 +- arch/arm/mach-omap2/prm2xxx_3xxx.c | 34 +-- arch/arm/mach-omap2/prm2xxx_3xxx.h | 12 +- arch/arm/mach-omap2/sdrc2xxx.c | 4 + arch/arm/mach-omap2/serial.c | 1 + arch/arm/plat-omap/mcbsp.c | 8 +- 19 files changed, 507 insertions(+), 478 deletions(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 954d11f3754..f51cffd1fc5 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) apll_mask = EN_APLL_LOCKED << clk->enable_bit; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); if ((cval & apll_mask) == apll_mask) return 0; /* apll already enabled */ cval &= ~apll_mask; cval |= apll_mask; - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, OMAP24XX_CM_IDLEST_VAL, clk->name); @@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) { u32 cval; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } /* Public data */ @@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) { u32 aplls, srate = 0; - aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 530a76bc4a6..4ae43922208 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) core_clk = omap2_get_dpll_rate(clk); - v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v &= OMAP24XX_CORE_CLK_SRC_MASK; if (v == CORE_CLK_SRC_32K) @@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; - core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ @@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) const struct dpll_data *dd; cur_rate = omap2xxx_clk_get_core_rate(dclk); - mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; if ((rate == (cur_rate / 2)) && (mult == 2)) { @@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index f49f47d7457..39f9d5a58d0 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) done_rate = CORE_CLK_SRC_DPLL; /* MPU divider */ - cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); /* dsp + iva1 div(2420), iva2.1(2430) */ - cm_write_mod_reg(prcm->cm_clksel_dsp, + omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, OMAP24XX_DSP_MOD, CM_CLKSEL); - cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); /* Major subsystem dividers */ - tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); if (cpu_is_omap2430()) - cm_write_mod_reg(prcm->cm_clksel_mdm, + omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, OMAP2430_MDM_MOD, CM_CLKSEL); /* x2 to enter omap2xxx_sdrc_init_params() */ diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a2142e0f1ef..da74f719d87 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -13,7 +13,6 @@ */ #undef DEBUG -#include #include #include #include @@ -30,7 +29,6 @@ #include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" #include #include @@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will wake up %s when %s wakes " "up\n", clkdm1->name, clkdm2->name); - prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will no longer wake up %s " "after %s wakes up\n", clkdm1->name, clkdm2->name); - prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic wkdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, (1 << clkdm2->dep_bit)); } @@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) atomic_set(&cd->wkdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); return 0; } @@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: will prevent %s from sleeping if %s " "is active\n", clkdm1->name, clkdm2->name); - cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) "sleeping if %s is active\n", clkdm1->name, clkdm2->name); - cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic sleepdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit)); } @@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) atomic_set(&cd->sleepdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); return 0; @@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { @@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 1c98dfc93a8..e3d598a4c62 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -29,37 +29,37 @@ static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; -u32 cm_read_mod_reg(s16 module, u16 idx) +u32 omap2_cm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(cm_base + module + idx); } -void cm_write_mod_reg(u32 val, s16 module, u16 idx) +void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) { __raw_writel(val, cm_base + module + idx); } /* Read-modify-write a register in a CM module. Caller must lock */ -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) { u32 v; - v = cm_read_mod_reg(module, idx); + v = omap2_cm_read_mod_reg(module, idx); v &= ~mask; v |= bits; - cm_write_mod_reg(v, module, idx); + omap2_cm_write_mod_reg(v, module, idx); return v; } -u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return cm_rmw_mod_reg_bits(bits, bits, module, idx); + return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); } -u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); + return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } /** @@ -90,7 +90,7 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) else BUG(); - omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; @@ -166,228 +166,238 @@ static struct omap3_cm_regs cm_context; void omap3_cm_save_context(void) { cm_context.iva2_cm_clksel1 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); cm_context.iva2_cm_clksel2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); cm_context.sgx_cm_clksel = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); cm_context.dss_cm_clksel = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); cm_context.cam_cm_clksel = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); cm_context.per_cm_clksel = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); cm_context.emu_cm_clksel = - cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); cm_context.emu_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); cm_context.pll_cm_autoidle2 = - cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); cm_context.pll_cm_clksel4 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); cm_context.pll_cm_clksel5 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); cm_context.pll_cm_clken2 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); cm_context.iva2_cm_fclken = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); - cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); + cm_context.iva2_cm_clken_pll = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); cm_context.core_cm_fclken1 = - cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); cm_context.core_cm_fclken3 = - cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); + omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); cm_context.sgx_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); cm_context.wkup_cm_fclken = - cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); cm_context.dss_cm_fclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); cm_context.cam_cm_fclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); cm_context.per_cm_fclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); cm_context.usbhost_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); cm_context.core_cm_iclken1 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); cm_context.core_cm_iclken2 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); cm_context.core_cm_iclken3 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); cm_context.sgx_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); cm_context.wkup_cm_iclken = - cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); cm_context.dss_cm_iclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); cm_context.cam_cm_iclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); cm_context.per_cm_iclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); cm_context.usbhost_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); cm_context.iva2_cm_autoidle2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); cm_context.mpu_cm_autoidle2 = - cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); cm_context.iva2_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); cm_context.mpu_cm_clkstctrl = - cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); cm_context.core_cm_clkstctrl = - cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); cm_context.sgx_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); cm_context.dss_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); cm_context.cam_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); cm_context.per_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); cm_context.neon_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); cm_context.usbhost_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL); cm_context.core_cm_autoidle1 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); cm_context.core_cm_autoidle2 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); cm_context.core_cm_autoidle3 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); cm_context.wkup_cm_autoidle = - cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); cm_context.dss_cm_autoidle = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); cm_context.cam_cm_autoidle = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); cm_context.per_cm_autoidle = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); cm_context.usbhost_cm_autoidle = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); cm_context.sgx_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); cm_context.dss_cm_sleepdep = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); cm_context.cam_cm_sleepdep = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); cm_context.per_cm_sleepdep = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); cm_context.usbhost_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP3430_CM_SLEEPDEP); cm_context.cm_clkout_ctrl = - cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); + omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); } void omap3_cm_restore_context(void) { - cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, - CM_CLKSEL1); - cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, - CM_CLKSEL2); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, + CM_CLKSEL2); __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); - cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, - CM_CLKSEL1); - cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, - OMAP3430ES2_CM_CLKSEL4); - cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, - OMAP3430ES2_CM_CLKSEL5); - cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, - OMAP3430ES2_CM_CLKEN2); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, + OMAP3430ES2_CM_CLKSEL4); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, + OMAP3430ES2_CM_CLKSEL5); + omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, + OMAP3430ES2_CM_CLKEN2); __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); - cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); - cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); - cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); - cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.usbhost_cm_fclken, - OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); - cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); - cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); - cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); - cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); - cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.usbhost_cm_iclken, - OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); - cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, - OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, - CM_AUTOIDLE1); - cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, - CM_AUTOIDLE3); - cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.usbhost_cm_autoidle, - OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); - cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, - OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, - OMAP3_CM_CLKOUT_CTRL_OFFSET); + omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKEN_PLL); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, + CM_FCLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, + OMAP3430ES2_CM_FCLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, + OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, + CM_ICLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, + CM_ICLKEN2); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, + CM_ICLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, + OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, + OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, + CM_AUTOIDLE1); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, + CM_AUTOIDLE3); + omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, + OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, + OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); } #endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index ce2582c1441..ff24edf54d3 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -104,14 +104,14 @@ #ifndef __ASSEMBLER__ -extern u32 cm_read_mod_reg(s16 module, u16 idx); -extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx); +extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); -extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); #endif diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 2506edfc4ac..61101e807df 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -252,13 +252,13 @@ void omap3_clear_scratchpad_contents(void) void __iomem *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); - if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & + if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & OMAP3430_GLOBAL_COLD_RST_MASK) { for ( ; offset <= max_offset; offset += 0x4) __raw_writel(0x0, (v_addr + offset)); - prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, - OMAP3430_GR_MOD, - OMAP3_PRM_RSTST_OFFSET); + omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, + OMAP3430_GR_MOD, + OMAP3_PRM_RSTST_OFFSET); } } @@ -300,32 +300,34 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.sdrc_block_offset = 0x64; /* Populate the PRCM block contents */ - prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_PRM_CLKSEL_OFFSET); + prcm_block_contents.prm_clksrc_ctrl = + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_CLKSRC_CTRL_OFFSET); + prcm_block_contents.prm_clksel = + omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_PRM_CLKSEL_OFFSET); prcm_block_contents.cm_clksel_core = - cm_read_mod_reg(CORE_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); prcm_block_contents.cm_clksel_wkup = - cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = - cm_read_mod_reg(PLL_MOD, CM_CLKEN); + omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); prcm_block_contents.cm_autoidle_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.cm_clksel3_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); prcm_block_contents.cm_clken_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); prcm_block_contents.cm_autoidle_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.prcm_block_size = 0x0; /* Populate the SDRC block contents */ diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index cf5f3331af2..911cd2e68d4 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -38,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { .cpu_set_freq = omap_pm_cpu_set_freq, .cpu_get_freq = omap_pm_cpu_get_freq, #endif - .dsp_prm_read = prm_read_mod_reg, - .dsp_prm_write = prm_write_mod_reg, - .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, - .dsp_cm_read = cm_read_mod_reg, - .dsp_cm_write = cm_write_mod_reg, - .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, + .dsp_prm_read = omap2_prm_read_mod_reg, + .dsp_prm_write = omap2_prm_write_mod_reg, + .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits, + .dsp_cm_read = omap2_cm_read_mod_reg, + .dsp_cm_write = omap2_cm_write_mod_reg, + .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, }; static int __init omap_dsp_init(void) diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1f5d68beabf..1a4efb5e435 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -45,10 +45,10 @@ u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = prm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg) #define DUMP_CM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = cm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg) #define DUMP_PRM_REG(reg) \ regs[reg_count].name = #reg; \ regs[reg_count++].val = __raw_readl(reg) @@ -328,10 +328,10 @@ static void pm_dbg_regset_store(u32 *ptr) for (j = pm_dbg_reg_modules[i].low; j <= pm_dbg_reg_modules[i].high; j += 4) { if (pm_dbg_reg_modules[i].type == MOD_CM) - val = cm_read_mod_reg( + val = omap2_cm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); else - val = prm_read_mod_reg( + val = omap2_prm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); *(ptr++) = val; } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 8ea49dcaae4..bf0c36b239f 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -79,8 +79,8 @@ static int omap2_fclks_active(void) { u32 f1, f2; - f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); /* Ignore UART clocks. These are handled by UART core (serial.c) */ f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); @@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void) /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* * Set MPU powerdomain's next power state to RETENTION; @@ -167,30 +167,30 @@ no_sleep: clk_enable(osc_ck); /* clear CORE wake-up events */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); /* MPU domain wake events */ - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x01) - prm_write_mod_reg(0x01, OCP_MOD, + omap2_prm_write_mod_reg(0x01, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x20) - prm_write_mod_reg(0x20, OCP_MOD, + omap2_prm_write_mod_reg(0x20, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); /* Mask future PRCM-to-MPU interrupts */ - prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); } static int omap2_i2c_active(void) { u32 l; - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); } @@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void) u32 l; /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) return 0; /* Check for UART3. */ - l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); if (l & OMAP24XX_EN_UART3_MASK) return 0; if (sti_console_enabled) @@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void) * it is in retention mode. */ if (omap2_allow_mpu_retention()) { /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* Try to enter MPU retention */ - prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, + omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); only_idle = 1; } @@ -310,9 +310,9 @@ static int omap2_pm_suspend(void) { u32 wken_wkup, mir1; - wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); + wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); /* Mask GPT1 */ mir1 = omap_readl(0x480fe0a4); @@ -322,7 +322,7 @@ static int omap2_pm_suspend(void) omap2_enter_full_retention(); omap_writel(mir1, 0x480fe0a4); - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); return 0; } @@ -376,7 +376,7 @@ static void __init prcm_setup_regs(void) struct powerdomain *pwrdm; /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, + omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); /* @@ -415,87 +415,87 @@ static void __init prcm_setup_regs(void) clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | - OMAP24XX_AUTO_MAILBOXES_MASK | - OMAP24XX_AUTO_WDT4_MASK | - OMAP2420_AUTO_WDT3_MASK | - OMAP24XX_AUTO_MSPRO_MASK | - OMAP2420_AUTO_MMC_MASK | - OMAP24XX_AUTO_FAC_MASK | - OMAP2420_AUTO_EAC_MASK | - OMAP24XX_AUTO_HDQ_MASK | - OMAP24XX_AUTO_UART2_MASK | - OMAP24XX_AUTO_UART1_MASK | - OMAP24XX_AUTO_I2C2_MASK | - OMAP24XX_AUTO_I2C1_MASK | - OMAP24XX_AUTO_MCSPI2_MASK | - OMAP24XX_AUTO_MCSPI1_MASK | - OMAP24XX_AUTO_MCBSP2_MASK | - OMAP24XX_AUTO_MCBSP1_MASK | - OMAP24XX_AUTO_GPT12_MASK | - OMAP24XX_AUTO_GPT11_MASK | - OMAP24XX_AUTO_GPT10_MASK | - OMAP24XX_AUTO_GPT9_MASK | - OMAP24XX_AUTO_GPT8_MASK | - OMAP24XX_AUTO_GPT7_MASK | - OMAP24XX_AUTO_GPT6_MASK | - OMAP24XX_AUTO_GPT5_MASK | - OMAP24XX_AUTO_GPT4_MASK | - OMAP24XX_AUTO_GPT3_MASK | - OMAP24XX_AUTO_GPT2_MASK | - OMAP2420_AUTO_VLYNQ_MASK | - OMAP24XX_AUTO_DSS_MASK, - CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | - OMAP24XX_AUTO_SSI_MASK | - OMAP24XX_AUTO_USB_MASK, - CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | - OMAP24XX_AUTO_GPMC_MASK | - OMAP24XX_AUTO_SDMA_MASK, - CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | - OMAP24XX_AUTO_AES_MASK | - OMAP24XX_AUTO_RNG_MASK | - OMAP24XX_AUTO_SHA_MASK | - OMAP24XX_AUTO_DES_MASK, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, - CM_AUTOIDLE); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | + OMAP24XX_AUTO_MAILBOXES_MASK | + OMAP24XX_AUTO_WDT4_MASK | + OMAP2420_AUTO_WDT3_MASK | + OMAP24XX_AUTO_MSPRO_MASK | + OMAP2420_AUTO_MMC_MASK | + OMAP24XX_AUTO_FAC_MASK | + OMAP2420_AUTO_EAC_MASK | + OMAP24XX_AUTO_HDQ_MASK | + OMAP24XX_AUTO_UART2_MASK | + OMAP24XX_AUTO_UART1_MASK | + OMAP24XX_AUTO_I2C2_MASK | + OMAP24XX_AUTO_I2C1_MASK | + OMAP24XX_AUTO_MCSPI2_MASK | + OMAP24XX_AUTO_MCSPI1_MASK | + OMAP24XX_AUTO_MCBSP2_MASK | + OMAP24XX_AUTO_MCBSP1_MASK | + OMAP24XX_AUTO_GPT12_MASK | + OMAP24XX_AUTO_GPT11_MASK | + OMAP24XX_AUTO_GPT10_MASK | + OMAP24XX_AUTO_GPT9_MASK | + OMAP24XX_AUTO_GPT8_MASK | + OMAP24XX_AUTO_GPT7_MASK | + OMAP24XX_AUTO_GPT6_MASK | + OMAP24XX_AUTO_GPT5_MASK | + OMAP24XX_AUTO_GPT4_MASK | + OMAP24XX_AUTO_GPT3_MASK | + OMAP24XX_AUTO_GPT2_MASK | + OMAP2420_AUTO_VLYNQ_MASK | + OMAP24XX_AUTO_DSS_MASK, + CORE_MOD, CM_AUTOIDLE1); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | + OMAP24XX_AUTO_SSI_MASK | + OMAP24XX_AUTO_USB_MASK, + CORE_MOD, CM_AUTOIDLE2); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | + OMAP24XX_AUTO_GPMC_MASK | + OMAP24XX_AUTO_SDMA_MASK, + CORE_MOD, CM_AUTOIDLE3); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | + OMAP24XX_AUTO_AES_MASK | + OMAP24XX_AUTO_RNG_MASK | + OMAP24XX_AUTO_SHA_MASK | + OMAP24XX_AUTO_DES_MASK, + CORE_MOD, OMAP24XX_CM_AUTOIDLE4); + + omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, + CM_AUTOIDLE); /* Put DPLL and both APLLs into autoidle mode */ - cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); - - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | - OMAP24XX_AUTO_WDT1_MASK | - OMAP24XX_AUTO_MPU_WDT_MASK | - OMAP24XX_AUTO_GPIOS_MASK | - OMAP24XX_AUTO_32KSYNC_MASK | - OMAP24XX_AUTO_GPT1_MASK, - WKUP_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | + (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT), + PLL_MOD, CM_AUTOIDLE); + + omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | + OMAP24XX_AUTO_WDT1_MASK | + OMAP24XX_AUTO_MPU_WDT_MASK | + OMAP24XX_AUTO_GPIOS_MASK | + OMAP24XX_AUTO_32KSYNC_MASK | + OMAP24XX_AUTO_GPT1_MASK, + WKUP_MOD, CM_AUTOIDLE); /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ - prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKSSETUP_OFFSET); + omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSSETUP_OFFSET); /* Configure automatic voltage transition */ - prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | - (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL_MASK | - (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | - (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); + omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_VOLTSETUP_OFFSET); + omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | + (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | + OMAP24XX_MEMRETCTRL_MASK | + (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | + (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), + OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, - WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, + WKUP_MOD, PM_WKEN); } static int __init omap2_pm_init(void) @@ -506,7 +506,7 @@ static int __init omap2_pm_init(void) return -ENODEV; printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Look up important powerdomains */ diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index cfff321c747..1ca6ef4c25b 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -105,12 +105,12 @@ static void omap3_enable_io_chain(void) int timeout = 0; if (omap_rev() >= OMAP3430_REV_ES3_1) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); /* Do a readback to assure write has been done */ - prm_read_mod_reg(WKUP_MOD, PM_WKEN); + omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); - while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & + while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & OMAP3430_ST_IO_CHAIN_MASK)) { timeout++; if (timeout > 1000) { @@ -118,7 +118,7 @@ static void omap3_enable_io_chain(void) "activation failed.\n"); return; } - prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, + omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } } @@ -127,7 +127,7 @@ static void omap3_enable_io_chain(void) static void omap3_disable_io_chain(void) { if (omap_rev() >= OMAP3430_REV_ES3_1) - prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } @@ -221,27 +221,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; int c = 0; - wkst = prm_read_mod_reg(module, wkst_off); - wkst &= prm_read_mod_reg(module, grpsel_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= omap2_prm_read_mod_reg(module, grpsel_off); if (wkst) { - iclk = cm_read_mod_reg(module, iclk_off); - fclk = cm_read_mod_reg(module, fclk_off); + iclk = omap2_cm_read_mod_reg(module, iclk_off); + fclk = omap2_cm_read_mod_reg(module, fclk_off); while (wkst) { clken = wkst; - cm_set_mod_reg_bits(clken, module, iclk_off); + omap2_cm_set_mod_reg_bits(clken, module, iclk_off); /* * For USBHOST, we don't know whether HOST1 or * HOST2 woke us up, so enable both f-clocks */ if (module == OMAP3430ES2_USBHOST_MOD) clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; - cm_set_mod_reg_bits(clken, module, fclk_off); - prm_write_mod_reg(wkst, module, wkst_off); - wkst = prm_read_mod_reg(module, wkst_off); + omap2_cm_set_mod_reg_bits(clken, module, fclk_off); + omap2_prm_write_mod_reg(wkst, module, wkst_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); c++; } - cm_write_mod_reg(iclk, module, iclk_off); - cm_write_mod_reg(fclk, module, fclk_off); + omap2_cm_write_mod_reg(iclk, module, iclk_off); + omap2_cm_write_mod_reg(fclk, module, fclk_off); } return c; @@ -284,9 +284,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) u32 irqenable_mpu, irqstatus_mpu; int c = 0; - irqenable_mpu = prm_read_mod_reg(OCP_MOD, + irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -307,10 +307,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) "no code to handle it (%08x)\n", irqstatus_mpu); } - prm_write_mod_reg(irqstatus_mpu, OCP_MOD, + omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -398,7 +398,7 @@ void omap_sram_idle(void) if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -471,7 +471,7 @@ void omap_sram_idle(void) omap_uart_resume_idle(0); omap_uart_resume_idle(1); if (core_next_state == PWRDM_POWER_OFF) - prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, + omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); } @@ -495,7 +495,8 @@ console_still_active: if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); omap3_disable_io_chain(); } @@ -633,21 +634,21 @@ static struct platform_suspend_ops omap_pm_ops = { static void __init omap3_iva_idle(void) { /* ensure IVA2 clock is disabled */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* if no clock activity, nothing else to do */ - if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & + if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & OMAP3430_CLKACTIVITY_IVA2_MASK)) return; /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ - cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, + omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Set IVA2 boot mode to 'idle' */ @@ -655,13 +656,13 @@ static void __init omap3_iva_idle(void) OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Disable IVA2 clock */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); @@ -685,10 +686,10 @@ static void __init omap3_d2d_idle(void) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | + omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, CORE_MOD, OMAP2_RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } static void __init prcm_setup_regs(void) @@ -703,23 +704,23 @@ static void __init prcm_setup_regs(void) /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); - prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); if (omap_rev() > OMAP3430_REV_ES1_0) { - prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); } else - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); /* * Enable interface clock autoidle for all modules. * Note that in the long run this should be done by clockfw */ - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MODEM_MASK | OMAP3430ES2_AUTO_MMC3_MASK | OMAP3430ES2_AUTO_ICR_MASK | @@ -752,7 +753,7 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_SSI_MASK, CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_PKA_MASK | OMAP3430_AUTO_AES1_MASK | OMAP3430_AUTO_RNG_MASK | @@ -761,13 +762,13 @@ static void __init prcm_setup_regs(void) CORE_MOD, CM_AUTOIDLE2); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MAD2D_MASK | OMAP3430ES2_AUTO_USBTLL_MASK, CORE_MOD, CM_AUTOIDLE3); } - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_WDT2_MASK | OMAP3430_AUTO_WDT1_MASK | OMAP3430_AUTO_GPIO1_MASK | @@ -776,17 +777,17 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_GPT1_MASK, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_DSS_MASK, OMAP3430_DSS_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_CAM_MASK, OMAP3430_CAM_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | @@ -810,7 +811,7 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430ES2_AUTO_USBHOST_MASK, OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); @@ -822,16 +823,16 @@ static void __init prcm_setup_regs(void) * Set all plls to autoidle. This is needed until autoidle is * enabled by clockfw */ - cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | + omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), PLL_MOD, CM_AUTOIDLE); - cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, PLL_MOD, CM_AUTOIDLE2); @@ -840,31 +841,31 @@ static void __init prcm_setup_regs(void) * sys_clkreq. In the long run clock framework should * take care of this. */ - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 1 << OMAP_AUTOEXTCLKMODE_SHIFT, OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET); /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, WKUP_MOD, PM_WKEN); /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | OMAP3430_GRPSEL_GPT1_MASK | OMAP3430_GRPSEL_GPT12_MASK, WKUP_MOD, OMAP3430_PM_MPUGRPSEL); /* For some reason IO doesn't generate wakeup event even if * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, + omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); /* Enable PM_WKEN to support DSS LPR */ - prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, + omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(omap3630_en_uart4_mask | + omap2_prm_write_mod_reg(omap3630_en_uart4_mask | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | @@ -872,7 +873,7 @@ static void __init prcm_setup_regs(void) OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(omap3630_grpsel_uart4_mask | + omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | @@ -885,22 +886,22 @@ static void __init prcm_setup_regs(void) OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); /* Don't attach IVA interrupts */ - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); /* Clear any pending PRCM interrupts */ - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); omap3_iva_idle(); omap3_d2d_idle(); diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index 838ac758c51..b5e9e4d18b8 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -28,7 +28,7 @@ /* Common functions across OMAP2 and OMAP3 */ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { - prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; @@ -36,14 +36,16 @@ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP_POWERSTATE_MASK); } static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP_POWERSTATEST_MASK); } static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, @@ -53,8 +55,8 @@ static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); return 0; } @@ -66,8 +68,8 @@ static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); return 0; } @@ -78,7 +80,8 @@ static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, + m); } static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -87,7 +90,8 @@ static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, m); } static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) @@ -95,8 +99,8 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) u32 v; v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -112,7 +116,7 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); @@ -131,26 +135,30 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) /* Applicable only for OMAP3. Not supported on OMAP2 */ static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTPOWERSTATEENTERED_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTPOWERSTATEENTERED_MASK); } static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, - OMAP3430_LOGICSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); } static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, - OMAP3430_LOGICSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP3430_LOGICSTATEST_MASK); } static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTLOGICSTATEENTERED_MASK); } static int omap3_get_mem_bank_lastmemst_mask(u8 bank) @@ -177,26 +185,28 @@ static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap3_get_mem_bank_lastmemst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, m); } static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { - prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); + omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); return 0; } static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) { - return prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return omap2_prm_rmw_mod_reg_bits(0, + 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); } static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) { - return prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + 0, pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); } struct pwrdm_ops omap2_pwrdm_operations = { diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index dae767bf195..4c5ab1a2d44 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -25,7 +25,7 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { - prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -33,25 +33,25 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); } static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK); } static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP4430_LASTPOWERSTATEENTERED_MASK); } static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { - prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -59,7 +59,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { - prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, OMAP4430_LASTPOWERSTATEENTERED_MASK, pwrdm->prcm_offs, OMAP4_PM_PWSTST); return 0; @@ -70,7 +70,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) u32 v; v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -83,7 +83,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -96,7 +96,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -104,14 +104,15 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP4430_LOGICSTATEST_MASK); } static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, - OMAP4430_LOGICRETSTATE_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL, + OMAP4430_LOGICRETSTATE_MASK); } static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) @@ -120,7 +121,8 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + m); } static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -129,7 +131,8 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL, m); } static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) @@ -143,7 +146,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 68c541f98ad..c22e726de12 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -17,7 +17,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include + +#include #include #include #include @@ -30,10 +31,9 @@ #include "clock.h" #include "clock2xxx.h" #include "cm2xxx_3xxx.h" -#include "cm44xx.h" #include "prm2xxx_3xxx.h" #include "prm44xx.h" -#include "prcm44xx.h" +#include "prminst44xx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-44xx.h" #include "control.h" @@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; if (cpu_is_omap44xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; return 0; } @@ -75,9 +75,9 @@ void omap_prcm_arch_reset(char mode, const char *cmd) } /* XXX should be moved to some OMAP2/3 specific code */ - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP2_RM_RSTCTRL); - prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, + OMAP2_RM_RSTCTRL); + omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ } /** diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 3e1d36c83fc..ec0362574b5 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -25,49 +25,49 @@ #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" -u32 prm_read_mod_reg(s16 module, u16 idx) +u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(prm_base + module + idx); } -void prm_write_mod_reg(u32 val, s16 module, u16 idx) +void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) { __raw_writel(val, prm_base + module + idx); } /* Read-modify-write a register in a PRM module. Caller must lock */ -u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) { u32 v; - v = prm_read_mod_reg(module, idx); + v = omap2_prm_read_mod_reg(module, idx); v &= ~mask; v |= bits; - prm_write_mod_reg(v, module, idx); + omap2_prm_write_mod_reg(v, module, idx); return v; } /* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) { u32 v; - v = prm_read_mod_reg(domain, idx); + v = omap2_prm_read_mod_reg(domain, idx); v &= mask; v >>= __ffs(mask); return v; } -u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return prm_rmw_mod_reg_bits(bits, bits, module, idx); + return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); } -u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); + return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } @@ -86,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) return -EINVAL; - return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, + return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, (1 << shift)); } @@ -110,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) return -EINVAL; mask = 1 << shift; - prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); return 0; } @@ -140,15 +140,15 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) mask = 1 << shift; /* Check the current status to avoid de-asserting the line twice */ - if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) return -EEXIST; /* Clear the reset status by writing 1 to the status bit */ - prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); /* de-assert the reset control line */ - prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); /* wait the status to be set */ - omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, + omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, mask), MAX_MODULE_HARDRESET_WAIT, c); diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index ab28517c82c..53d44f6e373 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -230,12 +230,12 @@ #ifndef __ASSEMBLER__ /* Power/reset management domain register get/set */ -extern u32 prm_read_mod_reg(s16 module, u16 idx); -extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); -extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); +extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); /* These omap2_ PRM functions apply to both OMAP2 and 3 */ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 64778b6240c..ccdb010f169 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); + /* + * XXX These calls should be abstracted out through a + * prm2xxx.c function + */ if (cpu_is_omap2420()) __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); else diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 26770d80419..c8740ba4fba 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -490,6 +490,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) u32 wk_mask = 0; u32 padconf = 0; + /* XXX These PRM accesses do not belong here */ uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); switch (uart->num) { diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 95449b90074..b5a6e178a7f 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -236,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp) * Sidetone uses McBSP ICLK - which must not idle when sidetones * are enabled or sidetones start sounding ugly. */ - w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w &= ~(1 << (mcbsp->id - 2)); - cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); /* Enable McBSP Sidetone */ w = MCBSP_READ(mcbsp, SSELCR); @@ -265,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp) w = MCBSP_READ(mcbsp, SSELCR); MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); - w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w |= 1 << (mcbsp->id - 2); - cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); } static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) -- cgit v1.2.3-70-g09d2 From 1540f214065982e6cbc6b8da1fe65a15e358f7c5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:15 -0700 Subject: OMAP2+: clockdomain: move header file from plat-omap to mach-omap2 The OMAP clockdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/clockdomain.h to mach-omap2/clockdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access clockdomain code and data directly. DSPBridge also uses the clockdomain headers for some reason, so, modify it also. The DSPBridge code should not be including the clockdomain headers; these should be removed. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Omar Ramirez Luna Cc: Felipe Contreras Cc: Greg Kroah-Hartman Tested-by: Rajendra Nayak Tested-by: Santosh Shilimkar --- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 2 +- arch/arm/mach-omap2/clockdomain.h | 149 ++++++++++++++++++++++ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 2 +- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- arch/arm/mach-omap2/cpuidle34xx.c | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/pm-debug.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/pm24xx.c | 2 +- arch/arm/mach-omap2/pm34xx.c | 2 +- arch/arm/mach-omap2/powerdomain.c | 2 +- arch/arm/plat-omap/include/plat/clockdomain.h | 151 ----------------------- drivers/staging/tidspbridge/core/_tiomap.h | 7 +- 15 files changed, 167 insertions(+), 164 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomain.h delete mode 100644 arch/arm/plat-omap/include/plat/clockdomain.h (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index cda2f1da2e1..2a2f15213ad 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -24,7 +24,7 @@ #include #include -#include +#include "clockdomain.h" #include #include diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index e5605c21ad3..650bf685dd9 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -35,7 +35,7 @@ #include #include -#include +#include "clockdomain.h" #include /* clkdm_list contains all registered struct clockdomains */ diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h new file mode 100644 index 00000000000..372c6466986 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain.h @@ -0,0 +1,149 @@ +/* + * arch/arm/plat-omap/include/mach/clockdomain.h + * + * OMAP2/3 clockdomain framework functions + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H + +#include + +#include +#include +#include + +/* Clockdomain capability flags */ +#define CLKDM_CAN_FORCE_SLEEP (1 << 0) +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) +#define CLKDM_CAN_ENABLE_AUTO (1 << 2) +#define CLKDM_CAN_DISABLE_AUTO (1 << 3) + +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) + +/** + * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode + * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only + * @omap_chip: OMAP chip types that this autodep is valid on + * + * A clockdomain that should have wkdeps and sleepdeps added when a + * clockdomain should stay active in hwsup mode; and conversely, + * removed when the clockdomain should be allowed to go inactive in + * hwsup mode. + * + * Autodeps are deprecated and should be removed after + * omap_hwmod-based fine-grained module idle control is added. + */ +struct clkdm_autodep { + union { + const char *name; + struct clockdomain *ptr; + } clkdm; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clkdm_dep - encode dependencies between clockdomains + * @clkdm_name: clockdomain name + * @clkdm: pointer to the struct clockdomain of @clkdm_name + * @omap_chip: OMAP chip types that this dependency is valid on + * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake + * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle + * + * Statically defined. @clkdm is resolved from @clkdm_name at runtime and + * should not be pre-initialized. + * + * XXX Should also include hardware (fixed) dependencies. + */ +struct clkdm_dep { + const char *clkdm_name; + struct clockdomain *clkdm; + atomic_t wkdep_usecount; + atomic_t sleepdep_usecount; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clockdomain - OMAP clockdomain + * @name: clockdomain name + * @pwrdm: powerdomain containing this clockdomain + * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain + * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg + * @flags: Clockdomain capability flags + * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit + * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers + * @cm_inst: (OMAP4 only) CM instance register offset + * @clkdm_offs: (OMAP4 only) CM clockdomain register offset + * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up + * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact + * @omap_chip: OMAP chip types that this clockdomain is valid on + * @usecount: Usecount tracking + * @node: list_head to link all clockdomains together + * + * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) + * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance + * definitions (OMAP4 only) + * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance + * definitions (OMAP4 only) + */ +struct clockdomain { + const char *name; + union { + const char *name; + struct powerdomain *ptr; + } pwrdm; +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + const u16 clktrctrl_mask; +#endif + const u8 flags; + const u8 dep_bit; + const u8 prcm_partition; + const s16 cm_inst; + const u16 clkdm_offs; + struct clkdm_dep *wkdep_srcs; + struct clkdm_dep *sleepdep_srcs; + const struct omap_chip_id omap_chip; + atomic_t usecount; + struct list_head node; +}; + +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); +struct clockdomain *clkdm_lookup(const char *name); + +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), + void *user); +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); + +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); + +void omap2_clkdm_allow_idle(struct clockdomain *clkdm); +void omap2_clkdm_deny_idle(struct clockdomain *clkdm); + +int omap2_clkdm_wakeup(struct clockdomain *clkdm); +int omap2_clkdm_sleep(struct clockdomain *clkdm); + +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); + +extern void __init omap2_clockdomains_init(void); +extern void __init omap44xx_clockdomains_init(void); + +#endif diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 6e9ec49d637..e4a7133ea3b 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -35,7 +35,7 @@ #include #include -#include +#include "clockdomain.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 2d3d1ef2381..51920fc7fc5 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -26,7 +26,7 @@ #include #include -#include +#include "clockdomain.h" #include "cm1_44xx.h" #include "cm2_44xx.h" diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 0fb619c5258..f518270b3e8 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include "clockdomain.h" #include #include "pm.h" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index ba766576e03..545182d9faa 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -41,7 +41,7 @@ #include #include -#include +#include "clockdomain.h" #include #include diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 1312ce2913a..e1358ba5139 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -139,7 +139,7 @@ #include #include -#include +#include "clockdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1a4efb5e435..3f989896a36 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include "clockdomain.h" #include #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 6ec2ee12272..24228e9dd49 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -19,7 +19,7 @@ #include #include -#include +#include "clockdomain.h" static struct omap_device_pm_latency *pm_lats; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index bf0c36b239f..f6aef7687b8 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -51,7 +51,7 @@ #include "control.h" #include -#include +#include "clockdomain.h" #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state = PM_SUSPEND_ON; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1ca6ef4c25b..0fae3d6b76e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -31,7 +31,7 @@ #include #include -#include +#include "clockdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a76ad3f0ca6..7eb7ba49d6b 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -27,7 +27,7 @@ #include #include -#include +#include "clockdomain.h" #include #include "pm.h" diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h deleted file mode 100644 index e91ae92f217..00000000000 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/clockdomain.h - * - * OMAP2/3 clockdomain framework functions - * - * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation - * - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX This should be moved to mach-omap2/ at the earliest opportunity. - */ - -#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H -#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H - -#include - -#include -#include -#include - -/* Clockdomain capability flags */ -#define CLKDM_CAN_FORCE_SLEEP (1 << 0) -#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) -#define CLKDM_CAN_ENABLE_AUTO (1 << 2) -#define CLKDM_CAN_DISABLE_AUTO (1 << 3) - -#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) -#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) -#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) - -/** - * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode - * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only - * @omap_chip: OMAP chip types that this autodep is valid on - * - * A clockdomain that should have wkdeps and sleepdeps added when a - * clockdomain should stay active in hwsup mode; and conversely, - * removed when the clockdomain should be allowed to go inactive in - * hwsup mode. - * - * Autodeps are deprecated and should be removed after - * omap_hwmod-based fine-grained module idle control is added. - */ -struct clkdm_autodep { - union { - const char *name; - struct clockdomain *ptr; - } clkdm; - const struct omap_chip_id omap_chip; -}; - -/** - * struct clkdm_dep - encode dependencies between clockdomains - * @clkdm_name: clockdomain name - * @clkdm: pointer to the struct clockdomain of @clkdm_name - * @omap_chip: OMAP chip types that this dependency is valid on - * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake - * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle - * - * Statically defined. @clkdm is resolved from @clkdm_name at runtime and - * should not be pre-initialized. - * - * XXX Should also include hardware (fixed) dependencies. - */ -struct clkdm_dep { - const char *clkdm_name; - struct clockdomain *clkdm; - atomic_t wkdep_usecount; - atomic_t sleepdep_usecount; - const struct omap_chip_id omap_chip; -}; - -/** - * struct clockdomain - OMAP clockdomain - * @name: clockdomain name - * @pwrdm: powerdomain containing this clockdomain - * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain - * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg - * @flags: Clockdomain capability flags - * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit - * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers - * @cm_inst: (OMAP4 only) CM instance register offset - * @clkdm_offs: (OMAP4 only) CM clockdomain register offset - * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up - * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact - * @omap_chip: OMAP chip types that this clockdomain is valid on - * @usecount: Usecount tracking - * @node: list_head to link all clockdomains together - * - * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) - * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance - * definitions (OMAP4 only) - * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance - * definitions (OMAP4 only) - */ -struct clockdomain { - const char *name; - union { - const char *name; - struct powerdomain *ptr; - } pwrdm; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - const u16 clktrctrl_mask; -#endif - const u8 flags; - const u8 dep_bit; - const u8 prcm_partition; - const s16 cm_inst; - const u16 clkdm_offs; - struct clkdm_dep *wkdep_srcs; - struct clkdm_dep *sleepdep_srcs; - const struct omap_chip_id omap_chip; - atomic_t usecount; - struct list_head node; -}; - -void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); -struct clockdomain *clkdm_lookup(const char *name); - -int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), - void *user); -struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); - -int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); -int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); - -void omap2_clkdm_allow_idle(struct clockdomain *clkdm); -void omap2_clkdm_deny_idle(struct clockdomain *clkdm); - -int omap2_clkdm_wakeup(struct clockdomain *clkdm); -int omap2_clkdm_sleep(struct clockdomain *clkdm); - -int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); - -extern void __init omap2_clockdomains_init(void); -extern void __init omap44xx_clockdomains_init(void); - -#endif diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index 7fac488f7f4..a3190e74ff7 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -19,8 +19,13 @@ #ifndef _TIOMAP_ #define _TIOMAP_ +/* + * XXX These powerdomain.h/clockdomain.h includes are wrong and should + * be removed. No driver should call pwrdm_* or clkdm_* functions + * directly; they should rely on OMAP core code to do this. + */ #include -#include +#include /* * XXX These mach-omap2/ includes are wrong and should be removed. No * driver should read or write to PRM/CM registers directly; they -- cgit v1.2.3-70-g09d2 From 72e06d087204f3bc9acf281717b90ebf0b9731f7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:16 -0700 Subject: OMAP2+: powerdomain: move header file from plat-omap to mach-omap2 The OMAP powerdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/powerdomain.h to mach-omap2/powerdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access powerdomain code and data directly. As part of this process, remove the references to powerdomain data from the GPIO "driver" and the OMAP PM no-op layer, both in plat-omap. Change the DSPBridge code to point to the new location for the powerdomain headers. The DSPBridge code should not be including the powerdomain headers; these should be removed. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Omar Ramirez Luna Cc: Felipe Contreras Cc: Greg Kroah-Hartman --- arch/arm/mach-omap2/clockdomain.c | 2 +- arch/arm/mach-omap2/clockdomain.h | 2 +- arch/arm/mach-omap2/cpuidle34xx.c | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/pm-debug.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/pm.h | 2 +- arch/arm/mach-omap2/pm24xx.c | 4 +- arch/arm/mach-omap2/pm34xx.c | 6 +- arch/arm/mach-omap2/pm44xx.c | 2 +- arch/arm/mach-omap2/powerdomain-common.c | 1 - arch/arm/mach-omap2/powerdomain.c | 2 +- arch/arm/mach-omap2/powerdomain.h | 232 +++++++++++++++++++++++ arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 2 +- arch/arm/mach-omap2/powerdomain44xx.c | 3 +- arch/arm/mach-omap2/powerdomains.h | 30 --- arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 4 +- arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h | 2 +- arch/arm/mach-omap2/powerdomains2xxx_data.c | 3 +- arch/arm/mach-omap2/powerdomains3xxx_data.c | 3 +- arch/arm/mach-omap2/powerdomains44xx_data.c | 3 +- arch/arm/plat-omap/gpio.c | 5 +- arch/arm/plat-omap/include/plat/gpio.h | 2 +- arch/arm/plat-omap/include/plat/omap-pm.h | 2 - arch/arm/plat-omap/include/plat/powerdomain.h | 219 --------------------- arch/arm/plat-omap/omap-pm-noop.c | 2 - drivers/staging/tidspbridge/core/_tiomap.h | 2 +- 28 files changed, 259 insertions(+), 286 deletions(-) create mode 100644 arch/arm/mach-omap2/powerdomain.h delete mode 100644 arch/arm/mach-omap2/powerdomains.h delete mode 100644 arch/arm/plat-omap/include/plat/powerdomain.h (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 650bf685dd9..e20b98636ab 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -34,7 +34,7 @@ #include "prcm44xx.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 372c6466986..de3faa20b46 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -18,7 +18,7 @@ #include -#include +#include "powerdomain.h" #include #include diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f518270b3e8..f3e043fe5eb 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -27,7 +27,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 545182d9faa..e66687b0b9d 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -39,7 +39,7 @@ #include "io.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e1358ba5139..12856eb7b17 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -140,7 +140,7 @@ #include #include #include "clockdomain.h" -#include +#include "powerdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 3f989896a36..e535082b0c2 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -29,7 +29,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 24228e9dd49..227a211921c 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -18,7 +18,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" static struct omap_device_pm_latency *pm_lats; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8b4f45eba1b..482df7fc158 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -11,7 +11,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H -#include +#include "powerdomain.h" extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index f6aef7687b8..2844b84f8d4 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -50,7 +50,7 @@ #include "pm.h" #include "control.h" -#include +#include "powerdomain.h" #include "clockdomain.h" #ifdef CONFIG_SUSPEND @@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); + omap2_gpio_prepare_for_idle(0); if (omap2_pm_debug) { omap2_pm_dump(0, 0, 0); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0fae3d6b76e..5efd1fb8c64 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -32,7 +32,7 @@ #include #include "clockdomain.h" -#include +#include "powerdomain.h" #include #include #include @@ -360,6 +360,7 @@ void omap_sram_idle(void) int mpu_next_state = PWRDM_POWER_ON; int per_next_state = PWRDM_POWER_ON; int core_next_state = PWRDM_POWER_ON; + int per_going_off; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; @@ -411,9 +412,10 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { + per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; omap_uart_prepare_idle(2); omap_uart_prepare_idle(3); - omap2_gpio_prepare_for_idle(per_next_state); + omap2_gpio_prepare_for_idle(per_going_off); if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 6aff9961e35..e9f4862c4de 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -16,7 +16,7 @@ #include #include -#include +#include "powerdomain.h" #include struct power_state { diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c index cb01c7a3689..171fccd208c 100644 --- a/arch/arm/mach-omap2/powerdomain-common.c +++ b/arch/arm/mach-omap2/powerdomain-common.c @@ -20,7 +20,6 @@ #include "cm-regbits-44xx.h" #include "prm-regbits-34xx.h" #include "prm-regbits-44xx.h" -#include "powerdomains.h" /* * OMAP3 and OMAP4 specific register bit initialisations diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 7eb7ba49d6b..06ef60eebeb 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -26,7 +26,7 @@ #include "prm44xx.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h new file mode 100644 index 00000000000..35b5b4800a4 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain.h @@ -0,0 +1,232 @@ +/* + * OMAP2/3/4 powerdomain control + * + * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This should be moved to the mach-omap2/ directory at the earliest + * opportunity. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H + +#include +#include + +#include + +#include + +/* Powerdomain basic power states */ +#define PWRDM_POWER_OFF 0x0 +#define PWRDM_POWER_RET 0x1 +#define PWRDM_POWER_INACTIVE 0x2 +#define PWRDM_POWER_ON 0x3 + +#define PWRDM_MAX_PWRSTS 4 + +/* Powerdomain allowable state bitfields */ +#define PWRSTS_ON (1 << PWRDM_POWER_ON) +#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_RET)) + +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) + + +/* Powerdomain flags */ +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits + * in MEM bank 1 position. This is + * true for OMAP3430 + */ +#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* + * support to transition from a + * sleep state to a lower sleep + * state without waking up the + * powerdomain + */ + +/* + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. + */ +#define PWRDM_MAX_MEM_BANKS 5 + +/* + * Maximum number of clockdomains that can be associated with a powerdomain. + * CORE powerdomain on OMAP4 is the worst case + */ +#define PWRDM_MAX_CLKDMS 9 + +/* XXX A completely arbitrary number. What is reasonable here? */ +#define PWRDM_TRANSITION_BAILOUT 100000 + +struct clockdomain; +struct powerdomain; + +/** + * struct powerdomain - OMAP powerdomain + * @name: Powerdomain name + * @omap_chip: represents the OMAP chip types containing this pwrdm + * @prcm_offs: the address offset from CM_BASE/PRM_BASE + * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs + * @pwrsts: Possible powerdomain power states + * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION + * @flags: Powerdomain flags + * @banks: Number of software-controllable memory banks in this powerdomain + * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION + * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON + * @pwrdm_clkdms: Clockdomains in this powerdomain + * @node: list_head linking all powerdomains + * @state: + * @state_counter: + * @timer: + * @state_timer: + * + * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. + */ +struct powerdomain { + const char *name; + const struct omap_chip_id omap_chip; + const s16 prcm_offs; + const u8 pwrsts; + const u8 pwrsts_logic_ret; + const u8 flags; + const u8 banks; + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; + const u8 prcm_partition; + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; + struct list_head node; + int state; + unsigned state_counter[PWRDM_MAX_PWRSTS]; + unsigned ret_logic_off_counter; + unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; + +#ifdef CONFIG_PM_DEBUG + s64 timer; + s64 state_timer[PWRDM_MAX_PWRSTS]; +#endif +}; + +/** + * struct pwrdm_ops - Arch specfic function implementations + * @pwrdm_set_next_pwrst: Set the target power state for a pd + * @pwrdm_read_next_pwrst: Read the target power state set for a pd + * @pwrdm_read_pwrst: Read the current power state of a pd + * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd + * @pwrdm_set_logic_retst: Set the logic state in RET for a pd + * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd + * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd + * @pwrdm_read_logic_pwrst: Read the current logic state of a pd + * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd + * @pwrdm_read_logic_retst: Read the logic state in RET for a pd + * @pwrdm_read_mem_pwrst: Read the current memory state of a pd + * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd + * @pwrdm_read_mem_retst: Read the memory state in RET for a pd + * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd + * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd + * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd + * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep + * @pwrdm_wait_transition: Wait for a pd state transition to complete + */ +struct pwrdm_ops { + int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); + int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); + int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); +}; + +void pwrdm_fw_init(void); +void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); + +struct powerdomain *pwrdm_lookup(const char *name); + +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); + +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, + int (*fn)(struct powerdomain *pwrdm, + struct clockdomain *clkdm)); + +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); + +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); + +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_logic_retst(struct powerdomain *pwrdm); +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); + +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); + +int pwrdm_wait_transition(struct powerdomain *pwrdm); + +int pwrdm_state_switch(struct powerdomain *pwrdm); +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); +int pwrdm_pre_transition(void); +int pwrdm_post_transition(void); +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); + +extern void omap2xxx_powerdomains_init(void); +extern void omap3xxx_powerdomains_init(void); +extern void omap44xx_powerdomains_init(void); + +extern struct pwrdm_ops omap2_pwrdm_operations; +extern struct pwrdm_ops omap3_pwrdm_operations; +extern struct pwrdm_ops omap4_pwrdm_operations; + +/* Common Internal functions used across OMAP rev's */ +extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); + +extern struct powerdomain wkup_omap2_pwrdm; +extern struct powerdomain gfx_omap2_pwrdm; + + +#endif diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index b5e9e4d18b8..d5233890370 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -18,8 +18,8 @@ #include +#include "powerdomain.h" #include "prm-regbits-34xx.h" -#include "powerdomains.h" #include "prm.h" #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 28bf5e3b000..a7880af4b3d 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -16,13 +16,12 @@ #include #include -#include +#include "powerdomain.h" #include #include "prm2xxx_3xxx.h" #include "prm44xx.h" #include "prminst44xx.h" #include "prm-regbits-44xx.h" -#include "powerdomains.h" static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h deleted file mode 100644 index f83adaf889e..00000000000 --- a/arch/arm/mach-omap2/powerdomains.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * OMAP2+ powerdomain prototypes - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H - -#include - -extern struct pwrdm_ops omap2_pwrdm_operations; -extern struct pwrdm_ops omap3_pwrdm_operations; -extern struct pwrdm_ops omap4_pwrdm_operations; - -/* Common Internal functions used across OMAP rev's */ -extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); -extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); -extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); - -extern struct powerdomain wkup_omap2_pwrdm; -extern struct powerdomain gfx_omap2_pwrdm; - -#endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index 14c6ef7e01e..5b4dd971320 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -45,13 +45,11 @@ * address offset is different between the C55 and C64 DSPs. */ -#include +#include "powerdomain.h" #include "prcm-common.h" #include "prm.h" -#include "powerdomains.h" - /* OMAP2/3-common powerdomains */ /* diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h index 45d684a3bf2..fa311669d53 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h @@ -14,7 +14,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H -#include +#include "powerdomain.h" extern struct powerdomain gfx_omap2_pwrdm; extern struct powerdomain wkup_omap2_pwrdm; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index e136895e0a3..9b1a3350057 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -14,9 +14,8 @@ #include #include -#include +#include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" -#include "powerdomains.h" #include "prcm-common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 1830c63ae67..e1bec562625 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -14,9 +14,8 @@ #include #include -#include +#include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" -#include "powerdomains.h" #include "prcm-common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c index 823f4770f94..5fdf485a022 100644 --- a/arch/arm/mach-omap2/powerdomains44xx_data.c +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -22,8 +22,7 @@ #include #include -#include -#include "powerdomains.h" +#include "powerdomain.h" #include "prcm-common.h" #include "prcm44xx.h" diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8d493b992e7..1f98e0b9484 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -29,7 +29,6 @@ #include #include #include -#include /* * OMAP1510 GPIO registers @@ -1864,7 +1863,7 @@ static struct sys_device omap_gpio_device = { static int workaround_enabled; -void omap2_gpio_prepare_for_idle(int power_state) +void omap2_gpio_prepare_for_idle(int off_mode) { int i, c = 0; int min = 0; @@ -1880,7 +1879,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_disable(bank->dbck); - if (power_state > PWRDM_POWER_OFF) + if (!off_mode) continue; /* If going to OFF, remove triggering for all diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 41ff2f8943f..d6f9fa0f62a 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -82,7 +82,7 @@ struct omap_gpio_platform_data { /* TODO: Analyze removing gpio_bank_count usage from driver code */ extern int gpio_bank_count; -extern void omap2_gpio_prepare_for_idle(int power_state); +extern void omap2_gpio_prepare_for_idle(int off_mode); extern void omap2_gpio_resume_after_idle(void); extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable); diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 62c3fe918ab..47d61107ccd 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -19,8 +19,6 @@ #include #include -#include "powerdomain.h" - /* * agent_id values for use with omap_pm_set_min_bus_tput(): * diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h deleted file mode 100644 index a0d3a30de9f..00000000000 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * OMAP2/3/4 powerdomain control - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX This should be moved to the mach-omap2/ directory at the earliest - * opportunity. - */ - -#ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN -#define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN - -#include -#include - -#include - -#include - -/* Powerdomain basic power states */ -#define PWRDM_POWER_OFF 0x0 -#define PWRDM_POWER_RET 0x1 -#define PWRDM_POWER_INACTIVE 0x2 -#define PWRDM_POWER_ON 0x3 - -#define PWRDM_MAX_PWRSTS 4 - -/* Powerdomain allowable state bitfields */ -#define PWRSTS_ON (1 << PWRDM_POWER_ON) -#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) -#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_ON)) - -#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_RET)) - -#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ - (1 << PWRDM_POWER_ON)) - -#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) - - -/* Powerdomain flags */ -#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ -#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits - * in MEM bank 1 position. This is - * true for OMAP3430 - */ -#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* - * support to transition from a - * sleep state to a lower sleep - * state without waking up the - * powerdomain - */ - -/* - * Number of memory banks that are power-controllable. On OMAP4430, the - * maximum is 5. - */ -#define PWRDM_MAX_MEM_BANKS 5 - -/* - * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP4 is the worst case - */ -#define PWRDM_MAX_CLKDMS 9 - -/* XXX A completely arbitrary number. What is reasonable here? */ -#define PWRDM_TRANSITION_BAILOUT 100000 - -struct clockdomain; -struct powerdomain; - -/** - * struct powerdomain - OMAP powerdomain - * @name: Powerdomain name - * @omap_chip: represents the OMAP chip types containing this pwrdm - * @prcm_offs: the address offset from CM_BASE/PRM_BASE - * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs - * @pwrsts: Possible powerdomain power states - * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION - * @flags: Powerdomain flags - * @banks: Number of software-controllable memory banks in this powerdomain - * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION - * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON - * @pwrdm_clkdms: Clockdomains in this powerdomain - * @node: list_head linking all powerdomains - * @state: - * @state_counter: - * @timer: - * @state_timer: - * - * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. - */ -struct powerdomain { - const char *name; - const struct omap_chip_id omap_chip; - const s16 prcm_offs; - const u8 pwrsts; - const u8 pwrsts_logic_ret; - const u8 flags; - const u8 banks; - const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; - const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; - const u8 prcm_partition; - struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; - struct list_head node; - int state; - unsigned state_counter[PWRDM_MAX_PWRSTS]; - unsigned ret_logic_off_counter; - unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; - -#ifdef CONFIG_PM_DEBUG - s64 timer; - s64 state_timer[PWRDM_MAX_PWRSTS]; -#endif -}; - -/** - * struct pwrdm_ops - Arch specfic function implementations - * @pwrdm_set_next_pwrst: Set the target power state for a pd - * @pwrdm_read_next_pwrst: Read the target power state set for a pd - * @pwrdm_read_pwrst: Read the current power state of a pd - * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd - * @pwrdm_set_logic_retst: Set the logic state in RET for a pd - * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd - * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd - * @pwrdm_read_logic_pwrst: Read the current logic state of a pd - * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd - * @pwrdm_read_logic_retst: Read the logic state in RET for a pd - * @pwrdm_read_mem_pwrst: Read the current memory state of a pd - * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd - * @pwrdm_read_mem_retst: Read the memory state in RET for a pd - * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd - * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd - * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd - * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep - * @pwrdm_wait_transition: Wait for a pd state transition to complete - */ -struct pwrdm_ops { - int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); - int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); - int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); - int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); - int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); - int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); - int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); -}; - -void pwrdm_fw_init(void); -void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); - -struct powerdomain *pwrdm_lookup(const char *name); - -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); -int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); - -int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, - int (*fn)(struct powerdomain *pwrdm, - struct clockdomain *clkdm)); - -int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); - -int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); -int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); - -int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); -int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - -int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_logic_retst(struct powerdomain *pwrdm); -int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); -int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); -int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); - -int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); -int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); -bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); - -int pwrdm_wait_transition(struct powerdomain *pwrdm); - -int pwrdm_state_switch(struct powerdomain *pwrdm); -int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); -int pwrdm_pre_transition(void); -int pwrdm_post_transition(void); -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); - -extern void omap2xxx_powerdomains_init(void); -extern void omap3xxx_powerdomains_init(void); -extern void omap44xx_powerdomains_init(void); - -#endif diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index ca75abb1806..19cb9f5a9f0 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -24,8 +24,6 @@ /* Interface documentation is in mach/omap-pm.h */ #include -#include - /* * Device-driver-originated constraints (via board-*.c files) */ diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index a3190e74ff7..1159a500f49 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -24,7 +24,7 @@ * be removed. No driver should call pwrdm_* or clkdm_* functions * directly; they should rely on OMAP core code to do this. */ -#include +#include #include /* * XXX These mach-omap2/ includes are wrong and should be removed. No -- cgit v1.2.3-70-g09d2 From 6081dc348f122cdb76093b2fc6cf5742c968cb69 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 21 Dec 2010 21:31:55 -0700 Subject: OMAP: PM noop: implement context loss count for non-omap_devices For devices which have not (yet) been converted to use omap_device, implement the context loss counter using the "brutal method" as originally proposed by Paul Walmsley[1]. The dummy context loss counter is incremented every time it is checked, but only when off-mode is enabled. When off-mode is disabled, the dummy counter stops incrementing. Tested on 36xx/Zoom3 using MMC driver, which is currently the only in-tree user of this API. This patch should be reverted after all devices are converted to using omap_device. [1] http://marc.info/?l=linux-omap&m=129176260000626&w=2 Signed-off-by: Kevin Hilman [paul@pwsan.com: fixed compile warning; fixed to compile on OMAP1] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/pm-debug.c | 5 ++++ arch/arm/plat-omap/include/plat/omap-pm.h | 2 ++ arch/arm/plat-omap/omap-pm-noop.c | 46 ++++++++++++++++++++++++++++++- 3 files changed, 52 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index e535082b0c2..125f56591fb 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -32,6 +32,7 @@ #include "powerdomain.h" #include "clockdomain.h" #include +#include #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" @@ -581,6 +582,10 @@ static int option_set(void *data, u64 val) *option = val; if (option == &enable_off_mode) { + if (val) + omap_pm_enable_off_mode(); + else + omap_pm_disable_off_mode(); if (cpu_is_omap34xx()) omap3_pm_off_mode_enable(val); } diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index c07bb44e9e5..c0a75205303 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -354,5 +354,7 @@ unsigned long omap_pm_cpu_get_freq(void); */ u32 omap_pm_get_dev_context_loss_count(struct device *dev); +void omap_pm_enable_off_mode(void); +void omap_pm_disable_off_mode(void); #endif diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index af58daddcf5..b0471bb2d47 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -26,6 +26,9 @@ #include #include +static bool off_mode_enabled; +static u32 dummy_context_loss_counter; + /* * Device-driver-originated constraints (via board-*.c files) */ @@ -280,10 +283,34 @@ unsigned long omap_pm_cpu_get_freq(void) return 0; } +/** + * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled + * + * Intended for use only by OMAP PM core code to notify this layer + * that off mode has been enabled. + */ +void omap_pm_enable_off_mode(void) +{ + off_mode_enabled = true; +} + +/** + * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled + * + * Intended for use only by OMAP PM core code to notify this layer + * that off mode has been disabled. + */ +void omap_pm_disable_off_mode(void) +{ + off_mode_enabled = false; +} + /* * Device context loss tracking */ +#ifdef CONFIG_ARCH_OMAP2PLUS + u32 omap_pm_get_dev_context_loss_count(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -292,13 +319,30 @@ u32 omap_pm_get_dev_context_loss_count(struct device *dev) if (WARN_ON(!dev)) return 0; - count = omap_device_get_context_loss_count(pdev); + if (dev->parent == &omap_device_parent) { + count = omap_device_get_context_loss_count(pdev); + } else { + WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device", + dev_name(dev)); + if (off_mode_enabled) + dummy_context_loss_counter++; + count = dummy_context_loss_counter; + } + pr_debug("OMAP PM: context loss count for dev %s = %d\n", dev_name(dev), count); return count; } +#else + +u32 omap_pm_get_dev_context_loss_count(struct device *dev) +{ + return dummy_context_loss_counter; +} + +#endif /* Should be called before clk framework init */ int __init omap_pm_if_early_init(void) -- cgit v1.2.3-70-g09d2