From e5f9dec8ff5ff3f6254412abed1f68d758f6616b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 4 Dec 2012 22:55:15 +0800 Subject: ARM: imx6q: support WAIT mode using cpuidle Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver. As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the support for revision 1.2 with chicken bit set. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/mach-imx/clk-imx6q.c') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index c7e429bd32d..b30b65a8cce 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -54,8 +54,19 @@ #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) +#define CGPR 0x64 +#define BM_CGPR_CHICKEN_BIT (0x1 << 17) + static void __iomem *ccm_base; +void imx6q_set_chicken_bit(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_CHICKEN_BIT; + writel_relaxed(val, ccm_base + CGPR); +} + int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { u32 val = readl_relaxed(ccm_base + CLPCR); @@ -66,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) break; case WAIT_UNCLOCKED: val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; break; case STOP_POWER_ON: val |= 0x2 << BP_CLPCR_LPM; -- cgit v1.2.3-70-g09d2