diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/am335x-bone.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/am335x-evm.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/am33xx.dtsi | 47 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/configs/omap2plus_defconfig | 3 | ||||
| -rw-r--r-- | arch/arm/mach-at91/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-at91/board-csb337.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200_emac.h | 138 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mach-imx6q.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 31 | ||||
| -rw-r--r-- | arch/arm/net/bpf_jit_32.c | 29 | ||||
| -rw-r--r-- | arch/arm/net/bpf_jit_32.h | 2 |
12 files changed, 140 insertions, 149 deletions
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 2c338889df1..11b240c5d32 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -128,3 +128,11 @@ }; }; }; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 9f65f17ebdf..d6496440fce 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -236,3 +236,11 @@ }; }; }; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 20a3f29a6bf..c2f14e875eb 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -338,5 +338,52 @@ power = <250>; ti,hwmods = "usb_otg_hs"; }; + + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "cpgmac0"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + cpts_active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x4a100000 0x800 + 0x4a101200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges; + + davinci_mdio: mdio@4a101000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x4a101000 0x100>; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d907d062e5d..cce1d874c7a 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -596,6 +596,7 @@ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ >; }; @@ -849,8 +850,8 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; - clocks = <&clks 117>, <&clks 117>; - clock-names = "ipg", "ahb"; + clocks = <&clks 117>, <&clks 117>, <&clks 177>; + clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 62303043db9..a1dc5c071e7 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -240,3 +240,6 @@ CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_LIBCRC32C=y CONFIG_SOC_OMAP5=y +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_DAVINCI_CPDMA=y +CONFIG_TI_CPSW=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index e34c1bdb804..958358c91af 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -39,7 +39,6 @@ config SOC_AT91RM9200 config SOC_AT91SAM9260 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" select HAVE_AT91_DBGU0 - select HAVE_NET_MACB select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE @@ -57,7 +56,6 @@ config SOC_AT91SAM9263 bool "AT91SAM9263" select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL - select HAVE_NET_MACB select SOC_AT91SAM9 config SOC_AT91SAM9RL @@ -70,7 +68,6 @@ config SOC_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10 families" select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL - select HAVE_NET_MACB select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. @@ -80,7 +77,6 @@ config SOC_AT91SAM9X5 bool "AT91SAM9x5 family" select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL - select HAVE_NET_MACB select SOC_AT91SAM9 help Select this if you are using one of Atmel's AT91SAM9x5 family SoC. diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index 78e02507442..48a531e05be 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -53,6 +53,8 @@ static void __init csb337_init_early(void) static struct macb_platform_data __initdata csb337_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 0, + /* The CSB337 bootloader stores the MAC the wrong-way around */ + .rev_eth_addr = 1, }; static struct at91_usbh_data __initdata csb337_usbh_data = { diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h deleted file mode 100644 index b8260cd8041..00000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91rm9200_emac.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Ethernet MAC registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_EMAC_H -#define AT91RM9200_EMAC_H - -#define AT91_EMAC_CTL 0x00 /* Control Register */ -#define AT91_EMAC_LB (1 << 0) /* Loopback */ -#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ -#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ -#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ -#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ -#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ -#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ -#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ -#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ - -#define AT91_EMAC_CFG 0x04 /* Configuration Register */ -#define AT91_EMAC_SPD (1 << 0) /* Speed */ -#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ -#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ -#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ -#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ -#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ -#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ -#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ -#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ -#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ -#define AT91_EMAC_CLK_DIV8 (0 << 10) -#define AT91_EMAC_CLK_DIV16 (1 << 10) -#define AT91_EMAC_CLK_DIV32 (2 << 10) -#define AT91_EMAC_CLK_DIV64 (3 << 10) -#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ -#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ - -#define AT91_EMAC_SR 0x08 /* Status Register */ -#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ -#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ -#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ - -#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ - -#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ -#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ -#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ - -#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ -#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ -#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ -#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ -#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ -#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ -#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ - -#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ - -#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ -#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ -#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ -#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ - -#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ -#define AT91_EMAC_DONE (1 << 0) /* Management Done */ -#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ -#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ -#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ -#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ -#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ -#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ -#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ -#define AT91_EMAC_LINK (1 << 9) /* Link */ -#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ -#define AT91_EMAC_ABT (1 << 11) /* Abort */ - -#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ -#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ -#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ - -#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ -#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ -#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ -#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ -#define AT91_EMAC_RW_W (1 << 28) -#define AT91_EMAC_RW_R (2 << 28) -#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ - -/* - * Statistics Registers. - */ -#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ -#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ -#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ -#define AT91_EMAC_OK 0x4c /* Frames Received OK */ -#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ -#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ -#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ -#define AT91_EMAC_LCOL 0x5c /* Late Collision */ -#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ -#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ -#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ -#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ -#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ -#define AT91_EMAC_CDE 0x74 /* Code Error */ -#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ -#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ -#define AT91_EMAC_USF 0x80 /* Undersize Frame */ -#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ - -/* - * Address Registers. - */ -#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ -#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ -#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ -#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ -#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ -#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ -#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ -#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ -#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ -#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ - -#endif diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 978b6dd00de..cce33e433bd 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -117,6 +117,17 @@ static void __init imx6q_sabrelite_init(void) imx6q_sabrelite_cko1_setup(); } +static void __init imx6q_1588_init(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); + else + pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + +} static void __init imx6q_usb_init(void) { struct regmap *anatop; @@ -153,6 +164,7 @@ static void __init imx6q_init_machine(void) imx6q_pm_init(); imx6q_usb_init(); + imx6q_1588_init(); } static struct cpuidle_driver imx6q_cpuidle_driver = { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index ad8d43b3327..32820d89f5b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -674,6 +674,7 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = { .name = "cpgmac0", .class = &am33xx_cpgmac0_hwmod_class, .clkdm_name = "cpsw_125mhz_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .mpu_irqs = am33xx_cpgmac0_irqs, .main_clk = "cpsw_125mhz_gclk", .prcm = { @@ -685,6 +686,20 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = { }; /* + * mdio class + */ +static struct omap_hwmod_class am33xx_mdio_hwmod_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod am33xx_mdio_hwmod = { + .name = "davinci_mdio", + .class = &am33xx_mdio_hwmod_class, + .clkdm_name = "cpsw_125mhz_clkdm", + .main_clk = "cpsw_125mhz_gclk", +}; + +/* * dcan class */ static struct omap_hwmod_class am33xx_dcan_hwmod_class = { @@ -2501,6 +2516,21 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { .user = OCP_USER_MPU, }; +struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = { + { + .pa_start = 0x4A101000, + .pa_end = 0x4A101000 + SZ_256 - 1, + }, + { } +}; + +struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { + .master = &am33xx_cpgmac0_hwmod, + .slave = &am33xx_mdio_hwmod, + .addr = am33xx_mdio_addr_space, + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { { .pa_start = 0x48080000, @@ -3371,6 +3401,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__tptc2, &am33xx_l3_s__usbss, &am33xx_l4_hs__cpgmac0, + &am33xx_cpgmac0__mdio, NULL, }; diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index b6f305e3b90..a34f1e21411 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -16,6 +16,7 @@ #include <linux/netdevice.h> #include <linux/string.h> #include <linux/slab.h> +#include <linux/if_vlan.h> #include <asm/cacheflush.h> #include <asm/hwcap.h> @@ -168,6 +169,8 @@ static inline bool is_load_to_a(u16 inst) case BPF_S_ANC_MARK: case BPF_S_ANC_PROTOCOL: case BPF_S_ANC_RXHASH: + case BPF_S_ANC_VLAN_TAG: + case BPF_S_ANC_VLAN_TAG_PRESENT: case BPF_S_ANC_QUEUE: return true; default: @@ -646,6 +649,16 @@ load_ind: update_on_xread(ctx); emit(ARM_ORR_R(r_A, r_A, r_X), ctx); break; + case BPF_S_ALU_XOR_K: + /* A ^= K; */ + OP_IMM3(ARM_EOR, r_A, r_A, k, ctx); + break; + case BPF_S_ANC_ALU_XOR_X: + case BPF_S_ALU_XOR_X: + /* A ^= X */ + update_on_xread(ctx); + emit(ARM_EOR_R(r_A, r_A, r_X), ctx); + break; case BPF_S_ALU_AND_K: /* A &= K */ OP_IMM3(ARM_AND, r_A, r_A, k, ctx); @@ -762,11 +775,6 @@ b_epilogue: update_on_xread(ctx); emit(ARM_MOV_R(r_A, r_X), ctx); break; - case BPF_S_ANC_ALU_XOR_X: - /* A ^= X */ - update_on_xread(ctx); - emit(ARM_EOR_R(r_A, r_A, r_X), ctx); - break; case BPF_S_ANC_PROTOCOL: /* A = ntohs(skb->protocol) */ ctx->seen |= SEEN_SKB; @@ -810,6 +818,17 @@ b_epilogue: off = offsetof(struct sk_buff, rxhash); emit(ARM_LDR_I(r_A, r_skb, off), ctx); break; + case BPF_S_ANC_VLAN_TAG: + case BPF_S_ANC_VLAN_TAG_PRESENT: + ctx->seen |= SEEN_SKB; + BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2); + off = offsetof(struct sk_buff, vlan_tci); + emit(ARM_LDRH_I(r_A, r_skb, off), ctx); + if (inst->code == BPF_S_ANC_VLAN_TAG) + OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx); + else + OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx); + break; case BPF_S_ANC_QUEUE: ctx->seen |= SEEN_SKB; BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h index 7fa2f7d3cb9..afb84621ff6 100644 --- a/arch/arm/net/bpf_jit_32.h +++ b/arch/arm/net/bpf_jit_32.h @@ -69,6 +69,7 @@ #define ARM_INST_CMP_I 0x03500000 #define ARM_INST_EOR_R 0x00200000 +#define ARM_INST_EOR_I 0x02200000 #define ARM_INST_LDRB_I 0x05d00000 #define ARM_INST_LDRB_R 0x07d00000 @@ -135,6 +136,7 @@ #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) +#define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) #define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \ | (off)) |