1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/sdram-micron-mt29c4g48.h b/arch/arm/mach-omap2/sdram-micron-mt29c4g48.h
new file mode 100644
index 00000000000..aa012b090f9
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-micron-mt29c4g48.h
@@ -0,0 +1,63 @@
+/*
+ * SDRC register values for the Micron MT29C4G48MAYAPAKQ-5
+ *
+ * Copyright (C) 2015 Olio Devices
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Mattis Fjallstrom (mattis at oliodevices.com)
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT29C4G48
+#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT29C4G48
+
+#include "sdrc.h"
+
+/* Micron MT29C4G48MAYAPAKQ-5 */
+/* 5ns -> 200MHz */
+
+
+/* 5.4ns -> 185.185185185185 MHz */
+/* 6ns -> 166.666667 MHz */
+/* 7.5ns -> 133.33333333333 */
+
+static struct omap_sdrc_params mt29c4g48_sdrc_params[] = {
+	[0] = {
+		.rate        = 200000000,
+		.actim_ctrla = 0x7AE1B4C6,
+		.actim_ctrlb = 0x00021217,
+		.rfr_ctrl    = 0x0005E601,
+		.mr	         = 0x00000034,
+	},
+	[1] = {
+		.rate	     = 185185185,
+		.actim_ctrla = 0x72E1B4C6,
+		.actim_ctrlb = 0x00021215,
+		.rfr_ctrl    = 0x00057201,
+		.mr  	     = 0x00000034,
+	},
+	[2] = {
+        .rate	     = 166000000,
+        .actim_ctrla = 0x629DB4C6,
+		.actim_ctrlb = 0x00011113,
+		.rfr_ctrl    = 0x0004E201,
+		.mr	         = 0x00000034,
+	},
+	[3] = {
+		.rate	     = 133333333,
+		.actim_ctrla = 0x5259B485,
+		.actim_ctrlb = 0x0001110F,
+		.rfr_ctrl    = 0x0003DE01,
+		.mr	         = 0x00000034,
+	},
+	[4] = {
+		.rate	     = 0,
+	},
+};
+
+#endif