diff options
| -rw-r--r-- | arch/arc/plat-arcfpga/Kconfig | 32 | ||||
| -rw-r--r-- | arch/arc/plat-arcfpga/platform.c | 56 |
2 files changed, 88 insertions, 0 deletions
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig index 38752bfb91e..9912d9c107a 100644 --- a/arch/arc/plat-arcfpga/Kconfig +++ b/arch/arc/plat-arcfpga/Kconfig @@ -44,4 +44,36 @@ config ARC_SERIAL_BAUD help Baud rate for the ARC UART +menuconfig ARC_HAS_BVCI_LAT_UNIT + bool "BVCI Bus Latency Unit" + depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 + help + IP to add artifical latency to BVCI Bus Based FPGA builds. + The default latency (even worst case) for FPGA is non-realistic + (~10 SDRAM, ~5 SSRAM). + +config BVCI_LAT_UNITS + hex "Latency Unit(s) Bitmap" + default "0x0" + depends on ARC_HAS_BVCI_LAT_UNIT + help + There are multiple Latency Units corresponding to the many + interfaces of the system bus arbiter (both CPU side as well as + the peripheral side). + To add latency to ALL memory transaction, choose Unit 0, otherwise + for finer grainer - interface wise latency, specify a bitmap (1 bit + per unit) of all units. e.g. 1,2,12 will be 0x1003 + + Unit 0 - System Arb and Mem Controller + Unit 1 - I$ and System Bus + Unit 2 - D$ and System Bus + .. + Unit 12 - IDE Disk controller and System Bus + +config BVCI_LAT_CYCLES + int "Latency Value in cycles" + range 0 63 + default "30" + depends on ARC_HAS_BVCI_LAT_UNIT + endif diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c index 33bcac8bd6b..b7f63e3f3ca 100644 --- a/arch/arc/plat-arcfpga/platform.c +++ b/arch/arc/plat-arcfpga/platform.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> +#include <linux/io.h> #include <linux/console.h> #include <linux/of_platform.h> #include <asm/setup.h> @@ -19,6 +20,59 @@ #include <asm/clk.h> #include <plat/memmap.h> +/*-----------------------BVCI Latency Unit -----------------------------*/ + +#ifdef CONFIG_ARC_HAS_BVCI_LAT_UNIT + +int lat_cycles = CONFIG_BVCI_LAT_CYCLES; + +/* BVCI Bus Profiler: Latency Unit */ +static void __init setup_bvci_lat_unit(void) +{ +#define MAX_BVCI_UNITS 12 + + unsigned int i; + unsigned int *base = (unsigned int *)BVCI_LAT_UNIT_BASE; + const unsigned long units_req = CONFIG_BVCI_LAT_UNITS; + const unsigned int REG_UNIT = 21; + const unsigned int REG_VAL = 22; + + /* + * There are multiple Latency Units corresponding to the many + * interfaces of the system bus arbiter (both CPU side as well as + * the peripheral side). + * + * Unit 0 - System Arb and Mem Controller - adds latency to all + * memory trasactions + * Unit 1 - I$ and System Bus + * Unit 2 - D$ and System Bus + * .. + * Unit 12 - IDE Disk controller and System Bus + * + * The programmers model requires writing to lat_unit reg first + * and then the latency value (cycles) to lat_value reg + */ + + if (CONFIG_BVCI_LAT_UNITS == 0) { + writel(0, base + REG_UNIT); + writel(lat_cycles, base + REG_VAL); + pr_info("BVCI Latency for all Memory Transactions %d cycles\n", + lat_cycles); + } else { + for_each_set_bit(i, &units_req, MAX_BVCI_UNITS) { + writel(i + 1, base + REG_UNIT); /* loop is 0 based */ + writel(lat_cycles, base + REG_VAL); + pr_info("BVCI Latency for Unit[%d] = %d cycles\n", + (i + 1), lat_cycles); + } + } +} +#else +static void __init setup_bvci_lat_unit(void) +{ +} +#endif + /*----------------------- Platform Devices -----------------------------*/ static unsigned long arc_uart_info[] = { @@ -106,6 +160,8 @@ void __init arc_platform_early_init(void) { pr_info("[plat-arcfpga]: registering early dev resources\n"); + setup_bvci_lat_unit(); + arc_fpga_serial_init(); } |