CW integration and minnow bringup

  * create minnow machine type
  * create Android makefile
  * add pre-commit syntax check
  * enable -Werror
  * Add drivers: CPCAP, TPS65xxx, m4sensorhub, atmxt, lm3535,
                 usb gadget, minnow display, TI 12xx wireless

Change-Id: I7962f5e1256715f2452aed5a62a4f2f2383d5046

2 files changed, 1819 insertions, 0 deletions

diff --git a/include/linux/spi/cpcap-regbits.h b/include/linux/spi/cpcap-regbits.h
new file mode 100644
index 00000000000..bf3aa7e0d69
--- /dev/null
+++ b/include/linux/spi/cpcap-regbits.h
@@ -0,0 +1,957 @@
+#ifndef __CPCAP_REGBITS_H__
+#define __CPCAP_REGBITS_H__
+
+/*
+ * Copyright (C) 2007-2009 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+/*
+ * Register 0 - CPCAP_REG_INT_0 bits
+ */
+#define CPCAP_BIT_ID_GROUND_I		0x00008000
+#define CPCAP_BIT_ID_FLOAT_I		0x00004000
+#define CPCAP_BIT_CHRG_DET_I		0x00002000
+#define CPCAP_BIT_RVRS_CHRG_I		0x00001000
+#define CPCAP_BIT_VBUSOV_I		0x00000800
+#define CPCAP_BIT_MB2_I			0x00000400
+#define CPCAP_BIT_HS_I			0x00000200
+#define CPCAP_BIT_ADCDONE_I		0x00000100
+#define CPCAP_BIT_TS_I			0x00000080
+#define CPCAP_BIT_EOL_I			0x00000040
+#define CPCAP_BIT_LOWBPH_I		0x00000020
+#define CPCAP_BIT_SEC2PRI_I		0x00000010
+#define CPCAP_BIT_LOWBPL_I		0x00000008
+#define CPCAP_BIT_UNUSED_0_2_I		0x00000004
+#define CPCAP_BIT_PRIMAC_I		0x00000002
+#define CPCAP_BIT_HSCLK_I		0x00000001
+
+/*
+ * Register 1 - CPCAP_REG_INT_1 bits
+ */
+#define CPCAP_BIT_EXTMEMHD_I		0x00008000
+#define CPCAP_BIT_UART_ECHO_OVERRUN_I	0x00004000
+#define CPCAP_BIT_CHRG_SE1B_I		0x00002000
+#define CPCAP_BIT_SE0CONN_I		0x00001000
+#define CPCAP_BIT_PTT_I			0x00000800
+#define CPCAP_BIT_1HZ_I			0x00000400
+#define CPCAP_BIT_CLK_I			0x00000200
+#define CPCAP_BIT_ON2_I			0x00000100
+#define CPCAP_BIT_ON_I			0x00000080
+#define CPCAP_BIT_RVRS_MODE_I		0x00000040
+#define CPCAP_BIT_CHRGCURR2_I		0x00000020
+#define CPCAP_BIT_CHRGCURR1_I		0x00000010
+#define CPCAP_BIT_VBUSVLD_I		0x00000008
+#define CPCAP_BIT_SESSVLD_I		0x00000004
+#define CPCAP_BIT_SESSEND_I		0x00000002
+#define CPCAP_BIT_SE1_I			0x00000001
+
+/*
+ * Register 2  CPCAP_REG_INT_2 -  bits
+ */
+#define CPCAP_BIT_USBDPLLCLK_I		0x00008000
+#define CPCAP_BIT_PWRGOOD_I		0x00004000
+#define CPCAP_BIT_UCRESET_I		0x00002000
+#define CPCAP_BIT_ONEWIRE3_I		0x00001000
+#define CPCAP_BIT_ONEWIRE2_I		0x00000800
+#define CPCAP_BIT_ONEWIRE1_I		0x00000400
+#define CPCAP_BIT_OPT_SEL_STATE_I	0x00000200
+#define CPCAP_BIT_OPT_SEL_DTCH_I	0x00000100
+#define CPCAP_BIT_TODA_I		0x00000080
+#define CPCAP_BIT_OFLOWSW_I		0x00000040
+#define CPCAP_BIT_PC_I			0x00000020
+#define CPCAP_BIT_DIETEMPH_I		0x00000010
+#define CPCAP_BIT_DIEPWRDWN_I		0x00000008
+#define CPCAP_BIT_SOFTRST_I		0x00000004
+#define CPCAP_BIT_SYSRSTRT_I		0x00000002
+#define CPCAP_BIT_WARM_I		0x00000001
+
+/*
+ * Register 3 - CPCAP_REG_INT_3  bits
+ */
+#define CPCAP_BIT_UNUSED_3_15_I		0x00008000
+#define CPCAP_BIT_UNUSED_3_14_I		0x00004000
+#define CPCAP_BIT_SPARE_3_13_I		0x00002000
+#define CPCAP_BIT_SPARE_3_12_I		0x00001000
+#define CPCAP_BIT_SPARE_3_11_I		0x00000800
+#define CPCAP_BIT_SPARE_3_10_I		0x00000400
+#define CPCAP_BIT_CC_CAL_I		0x00000200
+#define CPCAP_BIT_SECHALT_I		0x00000100
+#define CPCAP_BIT_PRIHALT_I		0x00000080
+#define CPCAP_BIT_BATTDETB_I		0x00000040
+#define CPCAP_BIT_SB_MAX_RETX_ERR_I	0x00000020
+#define CPCAP_BIT_GCAI_CURR2_I		0x00000010
+#define CPCAP_BIT_GCAI_CURR1_I		0x00000008
+#define CPCAP_BIT_UCBUSY_I		0x00000004
+#define CPCAP_BIT_DM_I			0x00000002
+#define CPCAP_BIT_DP_I			0x00000001
+
+/*
+ * Register 4 - CPCAP_REG_INTM1 bits
+ */
+#define CPCAP_BIT_ID_GROUND_M		0x00008000
+#define CPCAP_BIT_ID_FLOAT_M		0x00004000
+#define CPCAP_BIT_CHRG_DET_M		0x00002000
+#define CPCAP_BIT_RVRS_CHRG_M		0x00001000
+#define CPCAP_BIT_VBUSOV_M		0x00000800
+#define CPCAP_BIT_MB2_M			0x00000400
+#define CPCAP_BIT_HS_M			0x00000200
+#define CPCAP_BIT_ADCDONE_M		0x00000100
+#define CPCAP_BIT_TS_M			0x00000080
+#define CPCAP_BIT_EOL_M			0x00000040
+#define CPCAP_BIT_LOWBPH_M		0x00000020
+#define CPCAP_BIT_SEC2PRI_M		0x00000010
+#define CPCAP_BIT_LOWBPL_M		0x00000008
+#define CPCAP_BIT_UNUSED_4_2_M		0x00000004
+#define CPCAP_BIT_PRIMAC_M		0x00000002
+#define CPCAP_BIT_HSCLK_M		0x00000001
+
+/*
+ * Register 5 - CPCAP_REG_INTM2 bits
+ */
+#define CPCAP_BIT_EXTMEMHD_M		0x00008000
+#define CPCAP_BIT_UART_ECHO_OVERRUN_M	0x00004000
+#define CPCAP_BIT_CHRG_SE1B_M		0x00002000
+#define CPCAP_BIT_SE0CONN_M		0x00001000
+#define CPCAP_BIT_PTT_M			0x00000800
+#define CPCAP_BIT_1HZ_M			0x00000400
+#define CPCAP_BIT_CLK_M			0x00000200
+#define CPCAP_BIT_ON2_M			0x00000100
+#define CPCAP_BIT_ON_M			0x00000080
+#define CPCAP_BIT_RVRS_MODE_M		0x00000040
+#define CPCAP_BIT_CHRGCURR2_M		0x00000020
+#define CPCAP_BIT_CHRGCURR1_M		0x00000010
+#define CPCAP_BIT_VBUSVLD_M		0x00000008
+#define CPCAP_BIT_SESSVLD_M		0x00000004
+#define CPCAP_BIT_SESSEND_M		0x00000002
+#define CPCAP_BIT_SE1_M			0x00000001
+
+/*
+ * Register 6 - CPCAP_REG_INTM3 bits
+ */
+#define CPCAP_BIT_USBDPLLCLK_M		0x00008000
+#define CPCAP_BIT_PWRGOOD_M		0x00004000
+#define CPCAP_BIT_UCRESET_M		0x00002000
+#define CPCAP_BIT_ONEWIRE3_M		0x00001000
+#define CPCAP_BIT_ONEWIRE2_M		0x00000800
+#define CPCAP_BIT_ONEWIRE1_M		0x00000400
+#define CPCAP_BIT_OPT_SEL_STATE_M	0x00000200
+#define CPCAP_BIT_OPT_SEL_DTCH_M	0x00000100
+#define CPCAP_BIT_TODA_M		0x00000080
+#define CPCAP_BIT_OFLOWSW_M		0x00000040
+#define CPCAP_BIT_PC_M			0x00000020
+#define CPCAP_BIT_DIETEMPH_M		0x00000010
+#define CPCAP_BIT_DIEPWRDWN_M		0x00000008
+#define CPCAP_BIT_SOFTRST_M		0x00000004
+#define CPCAP_BIT_SYSRSTRT_M		0x00000002
+#define CPCAP_BIT_WARM_M		0x00000001
+
+/*
+ * Register 7 - CPCAP_REG_INTM4 bits
+ */
+#define CPCAP_BIT_UNUSED_7_15_M		0x00008000
+#define CPCAP_BIT_UNUSED_7_14_M		0x00004000
+#define CPCAP_BIT_SPARE_7_13_M		0x00002000
+#define CPCAP_BIT_SPARE_7_12_M		0x00001000
+#define CPCAP_BIT_SPARE_7_11_M		0x00000800
+#define CPCAP_BIT_SPARE_7_10_M		0x00000400
+#define CPCAP_BIT_CC_CAL_M		0x00000200
+#define CPCAP_BIT_SECHALT_M		0x00000100
+#define CPCAP_BIT_PRIHALT_M		0x00000080
+#define CPCAP_BIT_BATTDETB_M		0x00000040
+#define CPCAP_BIT_SB_MAX_RETX_ERR_M	0x00000020
+#define CPCAP_BIT_GCAI_CURR2_M		0x00000010
+#define CPCAP_BIT_GCAI_CURR1_M		0x00000008
+#define CPCAP_BIT_UCBUSY_M		0x00000004
+#define CPCAP_BIT_DM_M			0x00000002
+#define CPCAP_BIT_DP_M			0x00000001
+
+/*
+ * Register 8 - CPCAP_REG_INTS1 bits
+ */
+#define CPCAP_BIT_ID_GROUND_S		0x00008000
+#define CPCAP_BIT_ID_FLOAT_S		0x00004000
+#define CPCAP_BIT_CHRG_DET_S		0x00002000
+#define CPCAP_BIT_RVRS_CHRG_S		0x00001000
+#define CPCAP_BIT_VBUSOV_S		0x00000800
+#define CPCAP_BIT_MB2_S			0x00000400
+#define CPCAP_BIT_HS_S			0x00000200
+#define CPCAP_BIT_ADCDONE_S		0x00000100
+#define CPCAP_BIT_TS_S			0x00000080
+#define CPCAP_BIT_EOL_S			0x00000040
+#define CPCAP_BIT_LOWBPH_S		0x00000020
+#define CPCAP_BIT_SEC2PRI_S		0x00000010
+#define CPCAP_BIT_LOWBPL_S		0x00000008
+#define CPCAP_BIT_UNUSED_8_2_S		0x00000004
+#define CPCAP_BIT_PRIMAC_S		0x00000002
+#define CPCAP_BIT_HSCLK_S		0x00000001
+
+/*
+ * Register 9 - CPCAP_REG_INTS2 bits
+ */
+#define CPCAP_BIT_EXTMEMHD_S		0x00008000
+#define CPCAP_BIT_UART_ECHO_OVERRUN_S	0x00004000
+#define CPCAP_BIT_CHRG_SE1B_S		0x00002000
+#define CPCAP_BIT_SE0CONN_S		0x00001000
+#define CPCAP_BIT_PTT_S			0x00000800
+#define CPCAP_BIT_1HZ_S			0x00000400
+#define CPCAP_BIT_CLK_S			0x00000200
+#define CPCAP_BIT_ON2_S			0x00000100
+#define CPCAP_BIT_ON_S			0x00000080
+#define CPCAP_BIT_RVRS_MODE_S		0x00000040
+#define CPCAP_BIT_CHRGCURR2_S		0x00000020
+#define CPCAP_BIT_CHRGCURR1_S		0x00000010
+#define CPCAP_BIT_VBUSVLD_S		0x00000008
+#define CPCAP_BIT_SESSVLD_S		0x00000004
+#define CPCAP_BIT_SESSEND_S		0x00000002
+#define CPCAP_BIT_SE1_S			0x00000001
+
+/*
+ * Register 10 - CPCAP_REG_INTS3 bits
+ */
+#define CPCAP_BIT_USBDPLLCLK_S		0x00008000
+#define CPCAP_BIT_PWRGOOD_S		0x00004000
+#define CPCAP_BIT_UCRESET_S		0x00002000
+#define CPCAP_BIT_ONEWIRE3_S		0x00001000
+#define CPCAP_BIT_ONEWIRE2_S		0x00000800
+#define CPCAP_BIT_ONEWIRE1_S		0x00000400
+#define CPCAP_BIT_OPT_SEL_STATE_S	0x00000200
+#define CPCAP_BIT_OPT_SEL_DTCH_S	0x00000100
+#define CPCAP_BIT_TODA_S		0x00000080
+#define CPCAP_BIT_OFLOWSW_S		0x00000040
+#define CPCAP_BIT_PC_S			0x00000020
+#define CPCAP_BIT_DIETEMPH_S		0x00000010
+#define CPCAP_BIT_DIEPWRDWN_S		0x00000008
+#define CPCAP_BIT_SOFTRST_S		0x00000004
+#define CPCAP_BIT_SYSRSTRT_S		0x00000002
+#define CPCAP_BIT_WARM_S		0x00000001
+
+/*
+ * Register 11 - CPCAP_REG_INTS4 bits
+ */
+#define CPCAP_BIT_UNUSED_11_15_S	0x00008000
+#define CPCAP_BIT_UNUSED_11_14_S	0x00004000
+#define CPCAP_BIT_SPARE_11_13_S		0x00002000
+#define CPCAP_BIT_SPARE_11_12_S		0x00001000
+#define CPCAP_BIT_SPARE_11_11_S		0x00000800
+#define CPCAP_BIT_SPARE_11_10_S		0x00000400
+#define CPCAP_BIT_CC_CAL_S		0x00000200
+#define CPCAP_BIT_SECHALT_S		0x00000100
+#define CPCAP_BIT_PRIHALT_S		0x00000080
+#define CPCAP_BIT_BATTDETB_S		0x00000040
+#define CPCAP_BIT_SB_MAX_RETX_ERR_S	0x00000020
+#define CPCAP_BIT_GCAI_CURR2_S		0x00000010
+#define CPCAP_BIT_GCAI_CURR1_S		0x00000008
+#define CPCAP_BIT_UCBUSY_S		0x00000004
+#define CPCAP_BIT_DM_S			0x00000002
+#define CPCAP_BIT_DP_S			0x00000001
+
+/*
+ * Register 128 - CPCAP_REG_MI1 bits
+ */
+#define CPCAP_BIT_PRIMACRO_15_S		0x00008000
+#define CPCAP_BIT_PRIMACRO_14_S		0x00004000
+#define CPCAP_BIT_PRIMACRO_13_S		0x00002000
+#define CPCAP_BIT_PRIMACRO_12_S		0x00001000
+#define CPCAP_BIT_PRIMACRO_11_S		0x00000800
+#define CPCAP_BIT_PRIMACRO_10_S		0x00000400
+#define CPCAP_BIT_PRIMACRO_9_S		0x00000200
+#define CPCAP_BIT_PRIMACRO_8_S		0x00000100
+#define CPCAP_BIT_PRIMACRO_7_S		0x00000080
+#define CPCAP_BIT_PRIMACRO_6_S		0x00000040
+#define CPCAP_BIT_PRIMACRO_5_S		0x00000020
+#define CPCAP_BIT_PRIMACRO_4_S		0x00000010
+#define CPCAP_BIT_USEROFF_S		0x00000008
+#define CPCAP_BIT_PRIRAMR_S		0x00000004
+#define CPCAP_BIT_PRIRAMW_S		0x00000002
+#define CPCAP_BIT_PRIROMR_S		0x00000001
+
+/*
+ * Register 129 - CPCAP_REG_MIM1 bits
+ */
+#define CPCAP_BIT_PRIMACRO_15M		0x00008000
+#define CPCAP_BIT_PRIMACRO_14M		0x00004000
+#define CPCAP_BIT_PRIMACRO_13M		0x00002000
+#define CPCAP_BIT_PRIMACRO_12M		0x00001000
+#define CPCAP_BIT_PRIMACRO_11M		0x00000800
+#define CPCAP_BIT_PRIMACRO_10M		0x00000400
+#define CPCAP_BIT_PRIMACRO_9M		0x00000200
+#define CPCAP_BIT_PRIMACRO_8M		0x00000100
+#define CPCAP_BIT_PRIMACRO_7M		0x00000080
+#define CPCAP_BIT_PRIMACRO_6M		0x00000040
+#define CPCAP_BIT_PRIMACRO_5M		0x00000020
+#define CPCAP_BIT_PRIMACRO_4M		0x00000010
+#define CPCAP_BIT_USEROFFM		0x00000008
+#define CPCAP_BIT_PRIRAMRM		0x00000004
+#define CPCAP_BIT_PRIRAMWM		0x00000002
+#define CPCAP_BIT_PRIROMRM		0x00000001
+
+/*
+ * Register 130 - CPCAP_REG_MI2 bits
+ */
+#define CPCAP_BIT_PRIMACRO_15		0x00008000
+#define CPCAP_BIT_PRIMACRO_14		0x00004000
+#define CPCAP_BIT_PRIMACRO_13		0x00002000
+#define CPCAP_BIT_PRIMACRO_12		0x00001000
+#define CPCAP_BIT_PRIMACRO_11		0x00000800
+#define CPCAP_BIT_PRIMACRO_10		0x00000400
+#define CPCAP_BIT_PRIMACRO_9		0x00000200
+#define CPCAP_BIT_PRIMACRO_8		0x00000100
+#define CPCAP_BIT_PRIMACRO_7		0x00000080
+#define CPCAP_BIT_PRIMACRO_6		0x00000040
+#define CPCAP_BIT_PRIMACRO_5		0x00000020
+#define CPCAP_BIT_PRIMACRO_4		0x00000010
+#define CPCAP_BIT_USEROFF		0x00000008
+#define CPCAP_BIT_PRIRAMR		0x00000004
+#define CPCAP_BIT_PRIRAMW		0x00000002
+#define CPCAP_BIT_PRIROMR		0x00000001
+
+/*
+ * Register 131 - CPCAP_REG_MIM2 bits
+ */
+#define CPCAP_BIT_PRIMACRO_15S		0x00008000
+#define CPCAP_BIT_PRIMACRO_14S		0x00004000
+#define CPCAP_BIT_PRIMACRO_13S		0x00002000
+#define CPCAP_BIT_PRIMACRO_12S		0x00001000
+#define CPCAP_BIT_PRIMACRO_11S		0x00000800
+#define CPCAP_BIT_PRIMACRO_10S		0x00000400
+#define CPCAP_BIT_PRIMACRO_9S		0x00000200
+#define CPCAP_BIT_PRIMACRO_8S		0x00000100
+#define CPCAP_BIT_PRIMACRO_7S		0x00000080
+#define CPCAP_BIT_PRIMACRO_6S		0x00000040
+#define CPCAP_BIT_PRIMACRO_5S		0x00000020
+#define CPCAP_BIT_PRIMACRO_4S		0x00000010
+#define CPCAP_BIT_USEROFFS		0x00000008
+#define CPCAP_BIT_PRIRAMRS		0x00000004
+#define CPCAP_BIT_PRIRAMWS		0x00000002
+#define CPCAP_BIT_PRIROMRS		0x00000001
+
+/*
+ * Register 132 - CPCAP_REG_UCC1 bits
+ */
+#define CPCAP_BIT_UNUSED_132_15		0x00008000
+#define CPCAP_BIT_UNUSED_132_14		0x00004000
+#define CPCAP_BIT_UNUSED_132_13		0x00002000
+#define CPCAP_BIT_UNUSED_132_12		0x00001000
+#define CPCAP_BIT_PRI_GPIO6_2MAC10	0x00000800
+#define CPCAP_BIT_PRI_GPIO5_2MAC9	0x00000400
+#define CPCAP_BIT_PRI_GPIO4_2MAC8	0x00000200
+#define CPCAP_BIT_PRI_GPIO3_2MAC7	0x00000100
+#define CPCAP_BIT_PRI_GPIO2_2MAC6	0x00000080
+#define CPCAP_BIT_PRI_GPIO1_2MAC5	0x00000040
+#define CPCAP_BIT_PRI_GPIO0_2MAC4	0x00000020
+#define CPCAP_BIT_USEROFFCLK		0x00000010
+#define CPCAP_BIT_UO_MH_PFM_EN		0x00000008
+#define CPCAP_BIT_CNTRLSEC		0x00000004
+#define CPCAP_BIT_SCHDOVERRIDE		0x00000002
+#define CPCAP_BIT_PRIHALT		0x00000001
+
+/*
+ * Register 135 - CPCAP_REG_PC1 bits
+ */
+#define CPCAP_BIT_UNUSED_135_15		0x00008000
+#define CPCAP_BIT_UNUSED_135_14		0x00004000
+#define CPCAP_BIT_UNUSED_135_13		0x00002000
+#define CPCAP_BIT_UNUSED_135_12		0x00001000
+#define CPCAP_BIT_UNUSED_135_11		0x00000800
+#define CPCAP_BIT_UNUSED_135_10		0x00000400
+#define CPCAP_BIT_PC1_SC_SHTDWN_EN	0x00000200
+#define CPCAP_BIT_PC1_PCEN		0x00000100
+#define CPCAP_BIT_PC1_PCT7		0x00000080
+#define CPCAP_BIT_PC1_PCT6		0x00000040
+#define CPCAP_BIT_PC1_PCT5		0x00000020
+#define CPCAP_BIT_PC1_PCT4		0x00000010
+#define CPCAP_BIT_PC1_PCT3		0x00000008
+#define CPCAP_BIT_PC1_PCT2		0x00000004
+#define CPCAP_BIT_PC1_PCT1		0x00000002
+#define CPCAP_BIT_PC1_PCT0		0x00000001
+
+/*
+ * Register 138 - CPCAP_REG_PGC bits
+ */
+#define CPCAP_BIT_UNUSED_138_15		0x00008000
+#define CPCAP_BIT_UNUSED_138_14		0x00004000
+#define CPCAP_BIT_UNUSED_138_13		0x00002000
+#define CPCAP_BIT_UNUSED_138_12		0x00001000
+#define CPCAP_BIT_UNUSED_138_11		0x00000800
+#define CPCAP_BIT_UNUSED_138_10		0x00000400
+#define CPCAP_BIT_UNUSED_138_9		0x00000200
+#define CPCAP_BIT_REVENINV		0x00000100
+#define CPCAP_BIT_PRISTBYINV		0x00000080
+#define CPCAP_BIT_SYS_RST_MODE		0x00000040
+#define CPCAP_BIT_MAC_TIME_LONG		0x00000020
+#define CPCAP_BIT_PRI_UC_SUSPEND	0x00000010
+#define CPCAP_BIT_PRIWARMSTART		0x00000008
+#define CPCAP_BIT_PRIPRESVRAM		0x00000004
+#define CPCAP_BIT_SPI_PWRGT1EN		0x00000002
+#define CPCAP_BIT_SPI_PWRGT2EN		0x00000001
+
+/*
+ * Register 259 - CPCAP_REG_UCTM bits */
+#define CPCAP_BIT_UNUSED_259_15     0x00008000
+#define CPCAP_BIT_UNUSED_259_14     0x00004000
+#define CPCAP_BIT_UNUSED_259_13     0x00002000
+#define CPCAP_BIT_UNUSED_259_12     0x00001000
+#define CPCAP_BIT_UNUSED_259_11     0x00000800
+#define CPCAP_BIT_UNUSED_259_10     0x00000400
+#define CPCAP_BIT_UNUSED_259_9      0x00000200
+#define CPCAP_BIT_UNUSED_259_8      0x00000100
+#define CPCAP_BIT_UNUSED_259_7      0x00000080
+#define CPCAP_BIT_UNUSED_259_6      0x00000040
+#define CPCAP_BIT_UNUSED_259_5      0x00000020
+#define CPCAP_BIT_UNUSED_259_4      0x00000010
+#define CPCAP_BIT_UNUSED_259_3      0x00000008
+#define CPCAP_BIT_UNUSED_259_2      0x00000004
+#define CPCAP_BIT_UNUSED_259_1      0x00000002
+#define CPCAP_BIT_UCTM              0x00000001
+
+/*
+ * Register 266 - CPCAP_REG_VAL1 bits
+ */
+#define CPCAP_BIT_INVM_MC_MODE		0x00008000
+#define CPCAP_BIT_NVFLASH_MODE		0x00004000
+#define CPCAP_BIT_RECOVERY_MODE		0x00002000
+#define CPCAP_BIT_FASTBOOT_MODE		0x00001000
+#define CPCAP_BIT_BOOT_MODE		0x00000800
+#define CPCAP_BIT_BP2_ONLY_FLASH	0x00000400
+#define CPCAP_BIT_OUT_CHARGE_ONLY	0x00000200
+#define CPCAP_BIT_USB_BATT_RECOVERY	0x00000100
+#define CPCAP_BIT_PANIC			0x00000080
+#define CPCAP_BIT_BP_ONLY_FLASH		0x00000040
+#define CPCAP_BIT_WATCHDOG_RESET	0x00000020
+#define CPCAP_BIT_SOFT_RESET		0x00000010
+#define CPCAP_BIT_FLASH_FAIL		0x00000008
+#define CPCAP_BIT_FOTA_MODE		0x00000004
+#define CPCAP_BIT_AP_KERNEL_PANIC	0x00000002
+#define CPCAP_BIT_FLASH_MODE		0x00000001
+
+/*
+ * Register 385 - CPCAP_REG_SI2CC1
+ */
+#define CPCAP_BIT_CLK3M2_GATE_OVERRIDE	0x00000080
+
+/*
+ * Register 391 - CPCAP_REG_S3C
+ */
+#define CPCAP_BIT_SW3STBY		0x00000100
+
+/*
+ * Register 411 - CPCAP_REG_VUSB bits
+ */
+#define CPCAP_BIT_UNUSED_411_15		0x00008000
+#define CPCAP_BIT_UNUSED_411_14		0x00004000
+#define CPCAP_BIT_UNUSED_411_13		0x00002000
+#define CPCAP_BIT_UNUSED_411_12		0x00001000
+#define CPCAP_BIT_UNUSED_411_11		0x00000800
+#define CPCAP_BIT_UNUSED_411_10		0x00000400
+#define CPCAP_BIT_UNUSED_411_9		0x00000200
+#define CPCAP_BIT_VUSBSTBY		0x00000100
+#define CPCAP_BIT_UNUSED_411_7		0x00000080
+#define CPCAP_BIT_VUSB			0x00000040
+#define CPCAP_BIT_UNUSED_411_5		0x00000020
+#define CPCAP_BIT_VUSB_MODE2		0x00000010
+#define CPCAP_BIT_VUSB_MODE1		0x00000008
+#define CPCAP_BIT_VUSB_MODE0		0x00000004
+#define CPCAP_BIT_SPARE_411_1		0x00000002
+#define CPCAP_BIT_VBUS_SWITCH		0x00000001
+/*
+ * Register 512 - Audio Regulator and Bias Voltage
+ */
+
+#define CPCAP_BIT_AUDIO_LOW_PWR           0x00000040
+#define CPCAP_BIT_AUD_LOWPWR_SPEED        0x00000020
+#define CPCAP_BIT_VAUDIOPRISTBY           0x00000010
+#define CPCAP_BIT_VAUDIO_MODE1            0x00000004
+#define CPCAP_BIT_VAUDIO_MODE0            0x00000002
+#define CPCAP_BIT_V_AUDIO_EN              0x00000001
+
+/*
+ * Register 513 CODEC
+ */
+
+#define CPCAP_BIT_CDC_CLK2                0x00008000
+#define CPCAP_BIT_CDC_CLK1                0x00004000
+#define CPCAP_BIT_CDC_CLK0                0x00002000
+#define CPCAP_BIT_CDC_SR3                 0x00001000
+#define CPCAP_BIT_CDC_SR2                 0x00000800
+#define CPCAP_BIT_CDC_SR1                 0x00000400
+#define CPCAP_BIT_CDC_SR0                 0x00000200
+#define CPCAP_BIT_CDC_CLOCK_TREE_RESET    0x00000100
+#define CPCAP_BIT_MIC2_CDC_EN             0x00000080
+#define CPCAP_BIT_CDC_EN_RX               0x00000040
+#define CPCAP_BIT_DF_RESET                0x00000020
+#define CPCAP_BIT_MIC1_CDC_EN             0x00000010
+#define CPCAP_BIT_AUDOHPF_1		  0x00000008
+#define CPCAP_BIT_AUDOHPF_0		  0x00000004
+#define CPCAP_BIT_AUDIHPF_1		  0x00000002
+#define CPCAP_BIT_AUDIHPF_0		  0x00000001
+
+/*
+ * Register 514 CODEC Digital Audio Interface
+ */
+
+#define CPCAP_BIT_CDC_PLL_SEL             0x00008000
+#define CPCAP_BIT_CLK_IN_SEL              0x00002000
+#define CPCAP_BIT_DIG_AUD_IN              0x00001000
+#define CPCAP_BIT_CDC_CLK_EN              0x00000800
+#define CPCAP_BIT_CDC_DIG_AUD_FS1         0x00000400
+#define CPCAP_BIT_CDC_DIG_AUD_FS0         0x00000200
+#define CPCAP_BIT_MIC2_TIMESLOT2          0x00000100
+#define CPCAP_BIT_MIC2_TIMESLOT1          0x00000080
+#define CPCAP_BIT_MIC2_TIMESLOT0          0x00000040
+#define CPCAP_BIT_MIC1_RX_TIMESLOT2       0x00000020
+#define CPCAP_BIT_MIC1_RX_TIMESLOT1       0x00000010
+#define CPCAP_BIT_MIC1_RX_TIMESLOT0       0x00000008
+#define CPCAP_BIT_FS_INV                  0x00000004
+#define CPCAP_BIT_CLK_INV                 0x00000002
+#define CPCAP_BIT_SMB_CDC                 0x00000001
+
+/*
+ * Register 515 Stereo DAC
+ */
+
+#define CPCAP_BIT_FSYNC_CLK_IN_COMMON     0x00000800
+#define CPCAP_BIT_SLAVE_PLL_CLK_INPUT     0x00000400
+#define CPCAP_BIT_ST_CLOCK_TREE_RESET     0x00000200
+#define CPCAP_BIT_DF_RESET_ST_DAC         0x00000100
+#define CPCAP_BIT_ST_SR3                  0x00000080
+#define CPCAP_BIT_ST_SR2                  0x00000040
+#define CPCAP_BIT_ST_SR1                  0x00000020
+#define CPCAP_BIT_ST_SR0                  0x00000010
+#define CPCAP_BIT_ST_DAC_CLK2             0x00000008
+#define CPCAP_BIT_ST_DAC_CLK1             0x00000004
+#define CPCAP_BIT_ST_DAC_CLK0             0x00000002
+#define CPCAP_BIT_ST_DAC_EN               0x00000001
+
+/*
+ * Register 516 Stereo DAC Digital Audio Interface
+ */
+
+#define CPCAP_BIT_ST_L_TIMESLOT2          0x00002000
+#define CPCAP_BIT_ST_L_TIMESLOT1          0x00001000
+#define CPCAP_BIT_ST_L_TIMESLOT0          0x00000800
+#define CPCAP_BIT_ST_R_TIMESLOT2          0x00000400
+#define CPCAP_BIT_ST_R_TIMESLOT1          0x00000200
+#define CPCAP_BIT_ST_R_TIMESLOT0          0x00000100
+#define CPCAP_BIT_ST_DAC_CLK_IN_SEL       0x00000080
+#define CPCAP_BIT_ST_FS_INV               0x00000040
+#define CPCAP_BIT_ST_CLK_INV              0x00000020
+#define CPCAP_BIT_ST_DIG_AUD_FS1          0x00000010
+#define CPCAP_BIT_ST_DIG_AUD_FS0          0x00000008
+#define CPCAP_BIT_DIG_AUD_IN_ST_DAC       0x00000004
+#define CPCAP_BIT_ST_CLK_EN               0x00000002
+#define CPCAP_BIT_SMB_ST_DAC              0x00000001
+
+/*
+ * Register 517 - CPCAP_REG_TXI bits
+ */
+#define CPCAP_BIT_PTT_TH		0x00008000
+#define CPCAP_BIT_PTT_CMP_EN		0x00004000
+#define CPCAP_BIT_HS_ID_TX		0x00002000
+#define CPCAP_BIT_MB_ON2		0x00001000
+#define CPCAP_BIT_MB_ON1L		0x00000800
+#define CPCAP_BIT_MB_ON1R		0x00000400
+#define CPCAP_BIT_RX_L_ENCODE		0x00000200
+#define CPCAP_BIT_RX_R_ENCODE		0x00000100
+#define CPCAP_BIT_MIC2_MUX		0x00000080
+#define CPCAP_BIT_MIC2_PGA_EN		0x00000040
+#define CPCAP_BIT_CDET_DIS		0x00000020
+#define CPCAP_BIT_EMU_MIC_MUX		0x00000010
+#define CPCAP_BIT_HS_MIC_MUX		0x00000008
+#define CPCAP_BIT_MIC1_MUX		0x00000004
+#define CPCAP_BIT_MIC1_PGA_EN		0x00000002
+#define CPCAP_BIT_DLM			0x00000001
+
+/*
+ * Register 518 MIC PGA's
+ */
+#define CPCAP_BIT_MB_BIAS_R1              0x00000800
+#define CPCAP_BIT_MB_BIAS_R0              0x00000400
+#define CPCAP_BIT_MIC2_GAIN_4             0x00000200
+#define CPCAP_BIT_MIC2_GAIN_3             0x00000100
+#define CPCAP_BIT_MIC2_GAIN_2             0x00000080
+#define CPCAP_BIT_MIC2_GAIN_1             0x00000040
+#define CPCAP_BIT_MIC2_GAIN_0             0x00000020
+#define CPCAP_BIT_MIC1_GAIN_4             0x00000010
+#define CPCAP_BIT_MIC1_GAIN_3             0x00000008
+#define CPCAP_BIT_MIC1_GAIN_2             0x00000004
+#define CPCAP_BIT_MIC1_GAIN_1             0x00000002
+#define CPCAP_BIT_MIC1_GAIN_0             0x00000001
+
+/*
+ * Register 519 - CPCAP_REG_RXOA bits
+ */
+#define CPCAP_BIT_UNUSED_519_15		0x00008000
+#define CPCAP_BIT_UNUSED_519_14		0x00004000
+#define CPCAP_BIT_UNUSED_519_13		0x00002000
+#define CPCAP_BIT_STDAC_LOW_PWR_DISABLE	0x00001000
+#define CPCAP_BIT_HS_LOW_PWR		0x00000800
+#define CPCAP_BIT_HS_ID_RX		0x00000400
+#define CPCAP_BIT_ST_HS_CP_EN		0x00000200
+#define CPCAP_BIT_EMU_SPKR_R_EN		0x00000100
+#define CPCAP_BIT_EMU_SPKR_L_EN		0x00000080
+#define CPCAP_BIT_HS_L_EN		0x00000040
+#define CPCAP_BIT_HS_R_EN		0x00000020
+#define CPCAP_BIT_A4_LINEOUT_L_EN	0x00000010
+#define CPCAP_BIT_A4_LINEOUT_R_EN	0x00000008
+#define CPCAP_BIT_A2_LDSP_L_EN		0x00000004
+#define CPCAP_BIT_A2_LDSP_R_EN		0x00000002
+#define CPCAP_BIT_A1_EAR_EN		0x00000001
+
+/*
+ * Register 520 RX Volume Control
+ */
+#define CPCAP_BIT_VOL_EXT3                0x00008000
+#define CPCAP_BIT_VOL_EXT2                0x00004000
+#define CPCAP_BIT_VOL_EXT1                0x00002000
+#define CPCAP_BIT_VOL_EXT0                0x00001000
+#define CPCAP_BIT_VOL_DAC3                0x00000800
+#define CPCAP_BIT_VOL_DAC2                0x00000400
+#define CPCAP_BIT_VOL_DAC1                0x00000200
+#define CPCAP_BIT_VOL_DAC0                0x00000100
+#define CPCAP_BIT_VOL_DAC_LSB_1dB1        0x00000080
+#define CPCAP_BIT_VOL_DAC_LSB_1dB0        0x00000040
+#define CPCAP_BIT_VOL_CDC3                0x00000020
+#define CPCAP_BIT_VOL_CDC2                0x00000010
+#define CPCAP_BIT_VOL_CDC1                0x00000008
+#define CPCAP_BIT_VOL_CDC0                0x00000004
+#define CPCAP_BIT_VOL_CDC_LSB_1dB1        0x00000002
+#define CPCAP_BIT_VOL_CDC_LSB_1dB0        0x00000001
+
+/*
+ * Register 521 Codec to Output Amp Switches
+ */
+#define CPCAP_BIT_PGA_CDC_EN              0x00000400
+#define CPCAP_BIT_CDC_SW                  0x00000200
+#define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW   0x00000100
+#define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW   0x00000080
+#define CPCAP_BIT_ALEFT_HS_CDC_SW         0x00000040
+#define CPCAP_BIT_ARIGHT_HS_CDC_SW        0x00000020
+#define CPCAP_BIT_A4_LINEOUT_L_CDC_SW     0x00000010
+#define CPCAP_BIT_A4_LINEOUT_R_CDC_SW     0x00000008
+#define CPCAP_BIT_A2_LDSP_L_CDC_SW        0x00000004
+#define CPCAP_BIT_A2_LDSP_R_CDC_SW        0x00000002
+#define CPCAP_BIT_A1_EAR_CDC_SW           0x00000001
+
+/*
+ * Register 522 RX Stereo DAC to Output Amp Switches
+ */
+#define CPCAP_BIT_PGA_DAC_EN              0x00001000
+#define CPCAP_BIT_ST_DAC_SW               0x00000800
+#define CPCAP_BIT_MONO_DAC1               0x00000400
+#define CPCAP_BIT_MONO_DAC0               0x00000200
+#define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW   0x00000100
+#define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW   0x00000080
+#define CPCAP_BIT_ALEFT_HS_DAC_SW         0x00000040
+#define CPCAP_BIT_ARIGHT_HS_DAC_SW        0x00000020
+#define CPCAP_BIT_A4_LINEOUT_L_DAC_SW     0x00000010
+#define CPCAP_BIT_A4_LINEOUT_R_DAC_SW     0x00000008
+#define CPCAP_BIT_A2_LDSP_L_DAC_SW        0x00000004
+#define CPCAP_BIT_A2_LDSP_R_DAC_SW        0x00000002
+#define CPCAP_BIT_A1_EAR_DAC_SW           0x00000001
+
+/*
+ * Register 523 RX External PGA to Output Amp Switches
+ */
+#define CPCAP_BIT_PGA_EXT_L_EN            0x00004000
+#define CPCAP_BIT_PGA_EXT_R_EN            0x00002000
+#define CPCAP_BIT_PGA_IN_L_SW             0x00001000
+#define CPCAP_BIT_PGA_IN_R_SW             0x00000800
+#define CPCAP_BIT_MONO_EXT1               0x00000400
+#define CPCAP_BIT_MONO_EXT0               0x00000200
+#define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW   0x00000100
+#define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW   0x00000080
+#define CPCAP_BIT_ALEFT_HS_EXT_SW         0x00000040
+#define CPCAP_BIT_ARIGHT_HS_EXT_SW        0x00000020
+#define CPCAP_BIT_A4_LINEOUT_L_EXT_SW     0x00000010
+#define CPCAP_BIT_A4_LINEOUT_R_EXT_SW     0x00000008
+#define CPCAP_BIT_A2_LDSP_L_EXT_SW        0x00000004
+#define CPCAP_BIT_A2_LDSP_R_EXT_SW        0x00000002
+#define CPCAP_BIT_A1_EAR_EXT_SW           0x00000001
+
+/*
+ * Register 525 Loudspeaker Amplifier and Clock Configuration for Headset
+ */
+#define CPCAP_BIT_NCP_CLK_SYNC            0x00000080
+#define CPCAP_BIT_A2_CLK_SYNC             0x00000040
+#define CPCAP_BIT_A2_FREE_RUN             0x00000020
+#define CPCAP_BIT_A2_CLK2                 0x00000010
+#define CPCAP_BIT_A2_CLK1                 0x00000008
+#define CPCAP_BIT_A2_CLK0                 0x00000004
+#define CPCAP_BIT_A2_CLK_IN               0x00000002
+#define CPCAP_BIT_A2_CONFIG               0x00000001
+
+/*
+ * Register 641 - CPCAP_REG_CHRGR_1 bits
+ */
+#define CPCAP_BIT_UNUSED_641_15		0x00008000
+#define CPCAP_BIT_UNUSED_641_14		0x00004000
+#define CPCAP_BIT_CHRG_LED_EN		0x00002000
+#define CPCAP_BIT_RVRSMODE		0x00001000
+#define CPCAP_BIT_ICHRG_TR1		0x00000800
+#define CPCAP_BIT_ICHRG_TR0		0x00000400
+#define CPCAP_BIT_FET_OVRD		0x00000200
+#define CPCAP_BIT_FET_CTRL		0x00000100
+#define CPCAP_BIT_VCHRG3		0x00000080
+#define CPCAP_BIT_VCHRG2		0x00000040
+#define CPCAP_BIT_VCHRG1		0x00000020
+#define CPCAP_BIT_VCHRG0		0x00000010
+#define CPCAP_BIT_ICHRG3		0x00000008
+#define CPCAP_BIT_ICHRG2		0x00000004
+#define CPCAP_BIT_ICHRG1		0x00000002
+#define CPCAP_BIT_ICHRG0		0x00000001
+
+/*
+ * Register 768 - CPCAP_REG_ADCC1 bits
+ */
+#define CPCAP_BIT_ADEN_AUTO_CLR		0x00008000
+#define CPCAP_BIT_CAL_MODE		0x00004000
+#define CPCAP_BIT_ADC_CLK_SEL1		0x00002000
+#define CPCAP_BIT_ADC_CLK_SEL0		0x00001000
+#define CPCAP_BIT_ATOX         	        0x00000800
+#define CPCAP_BIT_ATO3		        0x00000400
+#define CPCAP_BIT_ATO2		        0x00000200
+#define CPCAP_BIT_ATO1		        0x00000100
+#define CPCAP_BIT_ATO0		        0x00000080
+#define CPCAP_BIT_ADA2		        0x00000040
+#define CPCAP_BIT_ADA1		        0x00000020
+#define CPCAP_BIT_ADA0		        0x00000010
+#define CPCAP_BIT_AD_SEL1		0x00000008
+#define CPCAP_BIT_RAND1		        0x00000004
+#define CPCAP_BIT_RAND0		        0x00000002
+#define CPCAP_BIT_ADEN        		0x00000001
+
+/*
+ * Register 769 - CPCAP_REG_ADCC2 bits
+ */
+#define CPCAP_BIT_CAL_FACTOR_ENABLE	0x00008000
+#define CPCAP_BIT_BATDETB_EN		0x00004000
+#define CPCAP_BIT_ADTRIG_ONESHOT	0x00002000
+#define CPCAP_BIT_ASC       		0x00001000
+#define CPCAP_BIT_ATOX_PS_FACTOR        0x00000800
+#define CPCAP_BIT_ADC_PS_FACTOR1        0x00000400
+#define CPCAP_BIT_ADC_PS_FACTOR0        0x00000200
+#define CPCAP_BIT_AD4_SELECT	        0x00000100
+#define CPCAP_BIT_ADC_BUSY	        0x00000080
+#define CPCAP_BIT_THERMBIAS_EN	        0x00000040
+#define CPCAP_BIT_ADTRIG_DIS	        0x00000020
+#define CPCAP_BIT_LIADC		        0x00000010
+#define CPCAP_BIT_TS_REFEN		0x00000008
+#define CPCAP_BIT_TS_M2		        0x00000004
+#define CPCAP_BIT_TS_M1		        0x00000002
+#define CPCAP_BIT_TS_M0        		0x00000001
+
+/*
+ * Register 896 - CPCAP_REG_USBC1 bits
+ */
+#define CPCAP_BIT_IDPULSE		0x00008000
+#define CPCAP_BIT_ID100KPU		0x00004000
+#define CPCAP_BIT_IDPUCNTRL		0x00002000
+#define CPCAP_BIT_IDPU			0x00001000
+#define CPCAP_BIT_IDPD			0x00000800
+#define CPCAP_BIT_VBUSCHRGTMR3		0x00000400
+#define CPCAP_BIT_VBUSCHRGTMR2		0x00000200
+#define CPCAP_BIT_VBUSCHRGTMR1		0x00000100
+#define CPCAP_BIT_VBUSCHRGTMR0		0x00000080
+#define CPCAP_BIT_VBUSPU		0x00000040
+#define CPCAP_BIT_VBUSPD		0x00000020
+#define CPCAP_BIT_DMPD			0x00000010
+#define CPCAP_BIT_DPPD			0x00000008
+#define CPCAP_BIT_DM1K5PU		0x00000004
+#define CPCAP_BIT_DP1K5PU		0X00000002
+#define CPCAP_BIT_DP150KPU		0x00000001
+
+/*
+ * Register 897 - CPCAP_REG_USBC2 bits
+ */
+#define CPCAP_BIT_ZHSDRV1		0x00008000
+#define CPCAP_BIT_ZHSDRV0		0x00004000
+#define CPCAP_BIT_DPLLCLKREQ		0x00002000
+#define CPCAP_BIT_SE0CONN		0x00001000
+#define CPCAP_BIT_UARTTXTRI		0x00000800
+#define CPCAP_BIT_UARTSWAP		0x00000400
+#define CPCAP_BIT_UARTMUX1		0x00000200
+#define CPCAP_BIT_UARTMUX0		0x00000100
+#define CPCAP_BIT_ULPISTPLOW		0x00000080
+#define CPCAP_BIT_TXENPOL		0x00000040
+#define CPCAP_BIT_USBXCVREN		0x00000020
+#define CPCAP_BIT_USBCNTRL		0x00000010
+#define CPCAP_BIT_USBSUSPEND		0x00000008
+#define CPCAP_BIT_EMUMODE2		0x00000004
+#define CPCAP_BIT_EMUMODE1		0x00000002
+#define CPCAP_BIT_EMUMODE0		0x00000001
+
+/*
+ * Register 898 - CPCAP_REG_USBC3 bits
+ */
+#define CPCAP_BIT_SPARE_898_15		0x00008000
+#define CPCAP_BIT_IHSTX03		0x00004000
+#define CPCAP_BIT_IHSTX02		0x00002000
+#define CPCAP_BIT_IHSTX01		0x00001000
+#define CPCAP_BIT_IHSTX0		0x00000800
+#define CPCAP_BIT_IDPU_SPI		0x00000400
+#define CPCAP_BIT_UNUSED_898_9		0x00000200
+#define CPCAP_BIT_VBUSSTBY_EN		0x00000100
+#define CPCAP_BIT_VBUSEN_SPI		0x00000080
+#define CPCAP_BIT_VBUSPU_SPI		0x00000040
+#define CPCAP_BIT_VBUSPD_SPI		0x00000020
+#define CPCAP_BIT_DMPD_SPI		0x00000010
+#define CPCAP_BIT_DPPD_SPI		0x00000008
+#define CPCAP_BIT_SUSPEND_SPI		0x00000004
+#define CPCAP_BIT_PU_SPI		0x00000002
+#define CPCAP_BIT_ULPI_SPI_SEL		0x00000001
+
+/*
+ * Register 941 - CPCAP_REG_GPIO0 bits
+ */
+#define CPCAP_BIT_GPIO0MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO0MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO0MACROML		0x00002000
+#define CPCAP_BIT_GPIO0MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_941_11		0x00000800
+#define CPCAP_BIT_UNUSED_941_10		0x00000400
+#define CPCAP_BIT_GPIO0VLEV		0x00000200
+#define CPCAP_BIT_UNUSED_941_8		0x00000100
+#define CPCAP_BIT_GPIO0MUX1		0x00000080
+#define CPCAP_BIT_GPIO0MUX0		0x00000040
+#define CPCAP_BIT_GPIO0OT		0x00000020
+#define CPCAP_BIT_SPARE_941_4		0x00000010
+#define CPCAP_BIT_GPIO0PUEN		0x00000008
+#define CPCAP_BIT_GPIO0DIR		0x00000004
+#define CPCAP_BIT_GPIO0DRV		0x00000002
+#define CPCAP_BIT_GPIO0S		0x00000001
+
+/*
+ * Register 943 - CPCAP_REG_GPIO1 bits
+ */
+#define CPCAP_BIT_GPIO1MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO1MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO1MACROML		0x00002000
+#define CPCAP_BIT_GPIO1MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_943_11		0x00000800
+#define CPCAP_BIT_UNUSED_943_10		0x00000400
+#define CPCAP_BIT_GPIO1VLEV		0x00000200
+#define CPCAP_BIT_UNUSED_943_8		0x00000100
+#define CPCAP_BIT_GPIO1MUX1		0x00000080
+#define CPCAP_BIT_GPIO1MUX0		0x00000040
+#define CPCAP_BIT_GPIO1OT		0x00000020
+#define CPCAP_BIT_SPARE_943_4		0x00000010
+#define CPCAP_BIT_GPIO1PUEN		0x00000008
+#define CPCAP_BIT_GPIO1DIR		0x00000004
+#define CPCAP_BIT_GPIO1DRV		0x00000002
+#define CPCAP_BIT_GPIO1S		0x00000001
+
+/*
+ * Register 945 - CPCAP_REG_GPIO2 bits
+ */
+#define CPCAP_BIT_GPIO2MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO2MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO2MACROML		0x00002000
+#define CPCAP_BIT_GPIO2MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_945_11		0x00000800
+#define CPCAP_BIT_UNUSED_945_10		0x00000400
+#define CPCAP_BIT_GPIO2VLEV		0x00000200
+#define CPCAP_BIT_UNUSED_945_8		0x00000100
+#define CPCAP_BIT_GPIO2MUX1		0x00000080
+#define CPCAP_BIT_GPIO2MUX0		0x00000040
+#define CPCAP_BIT_GPIO2OT		0x00000020
+#define CPCAP_BIT_SPARE_945_4		0x00000010
+#define CPCAP_BIT_GPIO2PUEN		0x00000008
+#define CPCAP_BIT_GPIO2DIR		0x00000004
+#define CPCAP_BIT_GPIO2DRV		0x00000002
+#define CPCAP_BIT_GPIO2S		0x00000001
+
+/*
+ * Register 947 - CPCAP_REG_GPIO3 bits
+ */
+#define CPCAP_BIT_GPIO3MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO3MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO3MACROML		0x00002000
+#define CPCAP_BIT_GPIO3MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_947_11		0x00000800
+#define CPCAP_BIT_UNUSED_947_10		0x00000400
+#define CPCAP_BIT_GPIO3VLEV		0x00000200
+#define CPCAP_BIT_UNUSED_947_8		0x00000100
+#define CPCAP_BIT_GPIO3MUX1		0x00000080
+#define CPCAP_BIT_GPIO3MUX0		0x00000040
+#define CPCAP_BIT_GPIO3OT		0x00000020
+#define CPCAP_BIT_SPARE_947_4		0x00000010
+#define CPCAP_BIT_GPIO3PUEN		0x00000008
+#define CPCAP_BIT_GPIO3DIR		0x00000004
+#define CPCAP_BIT_GPIO3DRV		0x00000002
+#define CPCAP_BIT_GPIO3S		0x00000001
+
+/*
+ * Register 949 - CPCAP_REG_GPIO4 bits
+ */
+#define CPCAP_BIT_GPIO4MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO4MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO4MACROML		0x00002000
+#define CPCAP_BIT_GPIO4MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_949_11		0x00000800
+#define CPCAP_BIT_UNUSED_949_10		0x00000400
+#define CPCAP_BIT_GPIO4VLEV		0x00000200
+#define CPCAP_BIT_UNUSED_949_8		0x00000100
+#define CPCAP_BIT_GPIO4MUX1		0x00000080
+#define CPCAP_BIT_GPIO4MUX0		0x00000040
+#define CPCAP_BIT_GPIO4OT		0x00000020
+#define CPCAP_BIT_SPARE_949_4		0x00000010
+#define CPCAP_BIT_GPIO4PUEN		0x00000008
+#define CPCAP_BIT_GPIO4DIR		0x00000004
+#define CPCAP_BIT_GPIO4DRV		0x00000002
+#define CPCAP_BIT_GPIO4S		0x00000001
+
+/*
+ * Register 951 - CPCAP_REG_GPIO5 bits
+ */
+#define CPCAP_BIT_GPIO5MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO5MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO5MACROML		0x00002000
+#define CPCAP_BIT_GPIO5MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_951_11		0x00000800
+#define CPCAP_BIT_UNUSED_951_10		0x00000400
+#define CPCAP_BIT_GPIO5VLEV		0x00000200
+#define CPCAP_BIT_GPIO5MUX2		0x00000100
+#define CPCAP_BIT_GPIO5MUX1		0x00000080
+#define CPCAP_BIT_GPIO5MUX0		0x00000040
+#define CPCAP_BIT_GPIO5OT		0x00000020
+#define CPCAP_BIT_SPARE_951_4		0x00000010
+#define CPCAP_BIT_GPIO5PUEN		0x00000008
+#define CPCAP_BIT_GPIO5DIR		0x00000004
+#define CPCAP_BIT_GPIO5DRV		0x00000002
+#define CPCAP_BIT_GPIO5S		0x00000001
+
+/*
+ * Register 953 - CPCAP_REG_GPIO6 bits
+ */
+#define CPCAP_BIT_GPIO6MACROINITL	0x00008000
+#define CPCAP_BIT_GPIO6MACROINITH	0x00004000
+#define CPCAP_BIT_GPIO6MACROML		0x00002000
+#define CPCAP_BIT_GPIO6MACROMH		0x00001000
+#define CPCAP_BIT_UNUSED_953_11		0x00000800
+#define CPCAP_BIT_UNUSED_953_10		0x00000400
+#define CPCAP_BIT_GPIO6VLEV		0x00000200
+#define CPCAP_BIT_GPIO6MUX2		0x00000100
+#define CPCAP_BIT_GPIO6MUX1		0x00000080
+#define CPCAP_BIT_GPIO6MUX0		0x00000040
+#define CPCAP_BIT_GPIO6OT		0x00000020
+#define CPCAP_BIT_SPARE_953_4		0x00000010
+#define CPCAP_BIT_GPIO6PUEN		0x00000008
+#define CPCAP_BIT_GPIO6DIR		0x00000004
+#define CPCAP_BIT_GPIO6DRV		0x00000002
+#define CPCAP_BIT_GPIO6S		0x00000001
+
+#endif /* __CPCAP_REGBITS_H__ */
diff --git a/include/linux/spi/cpcap.h b/include/linux/spi/cpcap.h
new file mode 100644
index 00000000000..9a00b1f5ccb
--- /dev/null
+++ b/include/linux/spi/cpcap.h
@@ -0,0 +1,862 @@
+#ifndef _LINUX_SPI_CPCAP_H
+#define _LINUX_SPI_CPCAP_H
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ *
+ */
+
+#include <linux/ioctl.h>
+#include <linux/rtc.h>
+#ifdef __KERNEL__
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/power_supply.h>
+#include <linux/platform_device.h>
+#endif
+
+#define CPCAP_DEV_NAME "cpcap"
+#define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1)
+
+#define CPCAP_IRQ_INT1_INDEX 0
+#define CPCAP_IRQ_INT2_INDEX 16
+#define CPCAP_IRQ_INT3_INDEX 32
+#define CPCAP_IRQ_INT4_INDEX 48
+#define CPCAP_IRQ_INT5_INDEX 64
+
+#define CPCAP_HWCFG_NUM       2    /* The number of hardware config words. */
+/*
+ * Tell the uC to setup the secondary standby bits for the regulators used.
+ */
+#define CPCAP_HWCFG0_NONE               0x0000
+#define CPCAP_HWCFG0_SEC_STBY_SW1       0x0001
+#define CPCAP_HWCFG0_SEC_STBY_SW2       0x0002
+#define CPCAP_HWCFG0_SEC_STBY_SW3       0x0004
+#define CPCAP_HWCFG0_SEC_STBY_SW4       0x0008
+#define CPCAP_HWCFG0_SEC_STBY_SW5       0x0010
+#define CPCAP_HWCFG0_SEC_STBY_VAUDIO    0x0020
+#define CPCAP_HWCFG0_SEC_STBY_VCAM      0x0040
+#define CPCAP_HWCFG0_SEC_STBY_VCSI      0x0080
+#define CPCAP_HWCFG0_SEC_STBY_VDAC      0x0100
+#define CPCAP_HWCFG0_SEC_STBY_VDIG      0x0200
+#define CPCAP_HWCFG0_SEC_STBY_VHVIO     0x0400
+#define CPCAP_HWCFG0_SEC_STBY_VPLL      0x0800
+#define CPCAP_HWCFG0_SEC_STBY_VRF1      0x1000
+#define CPCAP_HWCFG0_SEC_STBY_VRF2      0x2000
+#define CPCAP_HWCFG0_SEC_STBY_VRFREF    0x4000
+#define CPCAP_HWCFG0_SEC_STBY_VSDIO     0x8000
+
+#define CPCAP_HWCFG1_NONE               0x0000
+#define CPCAP_HWCFG1_SEC_STBY_VWLAN1    0x0001
+#define CPCAP_HWCFG1_SEC_STBY_VWLAN2    0x0002
+#define CPCAP_HWCFG1_SEC_STBY_VSIM      0x0004
+#define CPCAP_HWCFG1_SEC_STBY_VSIMCARD  0x0008
+#define CPCAP_HWCFG1_SEC_STBY_VUSB      0x0010
+/* Enable mapping of the PRI_STANDBY and SEC_STANDBY lines onto CPCAP GPIO. */
+#define CPCAP_HWCFG1_STBY_GPIO          0x1000
+
+#define CPCAP_WHISPER_MODE_PU 			0x00000001
+#define CPCAP_WHISPER_ENABLE_UART		0x00000002
+
+enum cpcap_regulator_id {
+	CPCAP_SW1,
+	CPCAP_SW2,
+	CPCAP_SW3,
+	CPCAP_SW4,
+	CPCAP_SW5,
+	CPCAP_VCAM,
+	CPCAP_VCSI,
+	CPCAP_VDAC,
+	CPCAP_VDIG,
+	CPCAP_VFUSE,
+	CPCAP_VHVIO,
+	CPCAP_VSDIO,
+	CPCAP_VPLL,
+	CPCAP_VRF1,
+	CPCAP_VRF2,
+	CPCAP_VRFREF,
+	CPCAP_VWLAN1,
+	CPCAP_VWLAN2,
+	CPCAP_VSIM,
+	CPCAP_VSIMCARD,
+	CPCAP_VVIB,
+	CPCAP_VUSB,
+	CPCAP_VAUDIO,
+
+	CPCAP_NUM_REGULATORS
+};
+
+/*
+ * Enumeration of all registers in the cpcap. Note that the register
+ * numbers on the CPCAP IC are not contiguous. The values of the enums below
+ * are not the actual register numbers.
+ */
+enum cpcap_reg {
+	CPCAP_REG_START,        /* Start of CPCAP registers. */
+
+	CPCAP_REG_INT1 = CPCAP_REG_START, /* Interrupt 1 */
+	CPCAP_REG_INT2,		/* Interrupt 2 */
+	CPCAP_REG_INT3,		/* Interrupt 3 */
+	CPCAP_REG_INT4,		/* Interrupt 4 */
+	CPCAP_REG_INTM1,	/* Interrupt Mask 1 */
+	CPCAP_REG_INTM2,	/* Interrupt Mask 2 */
+	CPCAP_REG_INTM3,	/* Interrupt Mask 3 */
+	CPCAP_REG_INTM4,	/* Interrupt Mask 4 */
+	CPCAP_REG_INTS1,	/* Interrupt Sense 1 */
+	CPCAP_REG_INTS2,	/* Interrupt Sense 2 */
+	CPCAP_REG_INTS3,	/* Interrupt Sense 3 */
+	CPCAP_REG_INTS4,	/* Interrupt Sense 4 */
+	CPCAP_REG_ASSIGN1,	/* Resource Assignment 1 */
+	CPCAP_REG_ASSIGN2,	/* Resource Assignment 2 */
+	CPCAP_REG_ASSIGN3,	/* Resource Assignment 3 */
+	CPCAP_REG_ASSIGN4,	/* Resource Assignment 4 */
+	CPCAP_REG_ASSIGN5,	/* Resource Assignment 5 */
+	CPCAP_REG_ASSIGN6,	/* Resource Assignment 6 */
+	CPCAP_REG_VERSC1,	/* Version Control 1 */
+	CPCAP_REG_VERSC2,	/* Version Control 2 */
+
+	CPCAP_REG_MI1,		/* Macro Interrupt 1 */
+	CPCAP_REG_MIM1,		/* Macro Interrupt Mask 1 */
+	CPCAP_REG_MI2,		/* Macro Interrupt 2 */
+	CPCAP_REG_MIM2,		/* Macro Interrupt Mask 2 */
+	CPCAP_REG_UCC1,		/* UC Control 1 */
+	CPCAP_REG_UCC2,		/* UC Control 2 */
+	CPCAP_REG_PC1,		/* Power Cut 1 */
+	CPCAP_REG_PC2,		/* Power Cut 2 */
+	CPCAP_REG_BPEOL,	/* BP and EOL */
+	CPCAP_REG_PGC,		/* Power Gate and Control */
+	CPCAP_REG_MT1,		/* Memory Transfer 1 */
+	CPCAP_REG_MT2,		/* Memory Transfer 2 */
+	CPCAP_REG_MT3,		/* Memory Transfer 3 */
+	CPCAP_REG_PF,		/* Print Format */
+
+	CPCAP_REG_SCC,		/* System Clock Control */
+	CPCAP_REG_SW1,		/* Stop Watch 1 */
+	CPCAP_REG_SW2,		/* Stop Watch 2 */
+	CPCAP_REG_UCTM,		/* UC Turbo Mode */
+	CPCAP_REG_TOD1,		/* Time of Day 1 */
+	CPCAP_REG_TOD2,		/* Time of Day 2 */
+	CPCAP_REG_TODA1,	/* Time of Day Alarm 1 */
+	CPCAP_REG_TODA2,	/* Time of Day Alarm 2 */
+	CPCAP_REG_DAY,		/* Day */
+	CPCAP_REG_DAYA,		/* Day Alarm */
+	CPCAP_REG_VAL1,		/* Validity 1 */
+	CPCAP_REG_VAL2,		/* Validity 2 */
+
+	CPCAP_REG_SDVSPLL,	/* Switcher DVS and PLL */
+	CPCAP_REG_SI2CC1,	/* Switcher I2C Control 1 */
+	CPCAP_REG_Si2CC2,	/* Switcher I2C Control 2 */
+	CPCAP_REG_S1C1,	        /* Switcher 1 Control 1 */
+	CPCAP_REG_S1C2,	        /* Switcher 1 Control 2 */
+	CPCAP_REG_S2C1,	        /* Switcher 2 Control 1 */
+	CPCAP_REG_S2C2,	        /* Switcher 2 Control 2 */
+	CPCAP_REG_S3C,	        /* Switcher 3 Control */
+	CPCAP_REG_S4C1,	        /* Switcher 4 Control 1 */
+	CPCAP_REG_S4C2,	        /* Switcher 4 Control 2 */
+	CPCAP_REG_S5C,	        /* Switcher 5 Control */
+	CPCAP_REG_S6C,	        /* Switcher 6 Control */
+	CPCAP_REG_VCAMC,	/* VCAM Control */
+	CPCAP_REG_VCSIC,	/* VCSI Control */
+	CPCAP_REG_VDACC,	/* VDAC Control */
+	CPCAP_REG_VDIGC,	/* VDIG Control */
+	CPCAP_REG_VFUSEC,	/* VFUSE Control */
+	CPCAP_REG_VHVIOC,	/* VHVIO Control */
+	CPCAP_REG_VSDIOC,	/* VSDIO Control */
+	CPCAP_REG_VPLLC,	/* VPLL Control */
+	CPCAP_REG_VRF1C,	/* VRF1 Control */
+	CPCAP_REG_VRF2C,	/* VRF2 Control */
+	CPCAP_REG_VRFREFC,	/* VRFREF Control */
+	CPCAP_REG_VWLAN1C,	/* VWLAN1 Control */
+	CPCAP_REG_VWLAN2C,	/* VWLAN2 Control */
+	CPCAP_REG_VSIMC,	/* VSIM Control */
+	CPCAP_REG_VVIBC,	/* VVIB Control */
+	CPCAP_REG_VUSBC,	/* VUSB Control */
+	CPCAP_REG_VUSBINT1C,	/* VUSBINT1 Control */
+	CPCAP_REG_VUSBINT2C,	/* VUSBINT2 Control */
+	CPCAP_REG_URT,		/* Useroff Regulator Trigger */
+	CPCAP_REG_URM1,		/* Useroff Regulator Mask 1 */
+	CPCAP_REG_URM2,		/* Useroff Regulator Mask 2 */
+
+	CPCAP_REG_VAUDIOC,	/* VAUDIO Control */
+	CPCAP_REG_CC,		/* Codec Control */
+	CPCAP_REG_CDI,		/* Codec Digital Interface */
+	CPCAP_REG_SDAC,		/* Stereo DAC */
+	CPCAP_REG_SDACDI,	/* Stereo DAC Digital Interface */
+	CPCAP_REG_TXI,		/* TX Inputs */
+	CPCAP_REG_TXMP,		/* TX MIC PGA's */
+	CPCAP_REG_RXOA,		/* RX Output Amplifiers */
+	CPCAP_REG_RXVC,		/* RX Volume Control */
+	CPCAP_REG_RXCOA,	/* RX Codec to Output Amps */
+	CPCAP_REG_RXSDOA,	/* RX Stereo DAC to Output Amps */
+	CPCAP_REG_RXEPOA,	/* RX External PGA to Output Amps */
+	CPCAP_REG_RXLL,		/* RX Low Latency */
+	CPCAP_REG_A2LA,		/* A2 Loudspeaker Amplifier */
+	CPCAP_REG_MIPIS1,	/* MIPI Slimbus 1 */
+	CPCAP_REG_MIPIS2,	/* MIPI Slimbus 2 */
+	CPCAP_REG_MIPIS3,	/* MIPI Slimbus 3. */
+	CPCAP_REG_LVAB,		/* LMR Volume and A4 Balanced. */
+
+	CPCAP_REG_CCC1,		/* Coulomb Counter Control 1 */
+	CPCAP_REG_CRM,		/* Charger and Reverse Mode */
+	CPCAP_REG_CCCC2,	/* Coincell and Coulomb Ctr Ctrl 2 */
+	CPCAP_REG_CCS1,		/* Coulomb Counter Sample 1 */
+	CPCAP_REG_CCS2,		/* Coulomb Counter Sample 2 */
+	CPCAP_REG_CCA1,		/* Coulomb Counter Accumulator 1 */
+	CPCAP_REG_CCA2,		/* Coulomb Counter Accumulator 2 */
+	CPCAP_REG_CCM,		/* Coulomb Counter Mode */
+	CPCAP_REG_CCO,		/* Coulomb Counter Offset */
+	CPCAP_REG_CCI,		/* Coulomb Counter Integrator */
+
+	CPCAP_REG_ADCC1,	/* A/D Converter Configuration 1 */
+	CPCAP_REG_ADCC2,	/* A/D Converter Configuration 2 */
+	CPCAP_REG_ADCD0,	/* A/D Converter Data 0 */
+	CPCAP_REG_ADCD1,	/* A/D Converter Data 1 */
+	CPCAP_REG_ADCD2,	/* A/D Converter Data 2 */
+	CPCAP_REG_ADCD3,	/* A/D Converter Data 3 */
+	CPCAP_REG_ADCD4,	/* A/D Converter Data 4 */
+	CPCAP_REG_ADCD5,	/* A/D Converter Data 5 */
+	CPCAP_REG_ADCD6,	/* A/D Converter Data 6 */
+	CPCAP_REG_ADCD7,	/* A/D Converter Data 7 */
+	CPCAP_REG_ADCAL1,	/* A/D Converter Calibration 1 */
+	CPCAP_REG_ADCAL2,	/* A/D Converter Calibration 2 */
+
+	CPCAP_REG_USBC1,	/* USB Control 1 */
+	CPCAP_REG_USBC2,	/* USB Control 2 */
+	CPCAP_REG_USBC3,	/* USB Control 3 */
+	CPCAP_REG_UVIDL,	/* ULPI Vendor ID Low */
+	CPCAP_REG_UVIDH,	/* ULPI Vendor ID High */
+	CPCAP_REG_UPIDL,	/* ULPI Product ID Low */
+	CPCAP_REG_UPIDH,	/* ULPI Product ID High */
+	CPCAP_REG_UFC1,		/* ULPI Function Control 1 */
+	CPCAP_REG_UFC2,		/* ULPI Function Control 2 */
+	CPCAP_REG_UFC3,		/* ULPI Function Control 3 */
+	CPCAP_REG_UIC1,		/* ULPI Interface Control 1 */
+	CPCAP_REG_UIC2,		/* ULPI Interface Control 2 */
+	CPCAP_REG_UIC3,		/* ULPI Interface Control 3 */
+	CPCAP_REG_USBOTG1,	/* USB OTG Control 1 */
+	CPCAP_REG_USBOTG2,	/* USB OTG Control 2 */
+	CPCAP_REG_USBOTG3,	/* USB OTG Control 3 */
+	CPCAP_REG_UIER1,	/* USB Interrupt Enable Rising 1 */
+	CPCAP_REG_UIER2,	/* USB Interrupt Enable Rising 2 */
+	CPCAP_REG_UIER3,	/* USB Interrupt Enable Rising 3 */
+	CPCAP_REG_UIEF1,	/* USB Interrupt Enable Falling 1 */
+	CPCAP_REG_UIEF2,	/* USB Interrupt Enable Falling 1 */
+	CPCAP_REG_UIEF3,	/* USB Interrupt Enable Falling 1 */
+	CPCAP_REG_UIS,		/* USB Interrupt Status */
+	CPCAP_REG_UIL,		/* USB Interrupt Latch */
+	CPCAP_REG_USBD,		/* USB Debug */
+	CPCAP_REG_SCR1,		/* Scratch 1 */
+	CPCAP_REG_SCR2,		/* Scratch 2 */
+	CPCAP_REG_SCR3,		/* Scratch 3 */
+	CPCAP_REG_VMC,		/* Video Mux Control */
+	CPCAP_REG_OWDC,		/* One Wire Device Control */
+	CPCAP_REG_GPIO0,	/* GPIO 0 Control */
+	CPCAP_REG_GPIO1,	/* GPIO 1 Control */
+	CPCAP_REG_GPIO2,	/* GPIO 2 Control */
+	CPCAP_REG_GPIO3,	/* GPIO 3 Control */
+	CPCAP_REG_GPIO4,	/* GPIO 4 Control */
+	CPCAP_REG_GPIO5,	/* GPIO 5 Control */
+	CPCAP_REG_GPIO6,	/* GPIO 6 Control */
+
+	CPCAP_REG_MDLC,		/* Main Display Lighting Control */
+	CPCAP_REG_KLC,		/* Keypad Lighting Control */
+	CPCAP_REG_ADLC,		/* Aux Display Lighting Control */
+	CPCAP_REG_REDC,		/* Red Triode Control */
+	CPCAP_REG_GREENC,	/* Green Triode Control */
+	CPCAP_REG_BLUEC,	/* Blue Triode Control */
+	CPCAP_REG_CFC,		/* Camera Flash Control */
+	CPCAP_REG_ABC,		/* Adaptive Boost Control */
+	CPCAP_REG_BLEDC,	/* Bluetooth LED Control */
+	CPCAP_REG_CLEDC,	/* Camera Privacy LED Control */
+
+	CPCAP_REG_OW1C,		/* One Wire 1 Command */
+	CPCAP_REG_OW1D,		/* One Wire 1 Data */
+	CPCAP_REG_OW1I,		/* One Wire 1 Interrupt */
+	CPCAP_REG_OW1IE,	/* One Wire 1 Interrupt Enable */
+	CPCAP_REG_OW1,		/* One Wire 1 Control */
+	CPCAP_REG_OW2C,		/* One Wire 2 Command */
+	CPCAP_REG_OW2D,		/* One Wire 2 Data */
+	CPCAP_REG_OW2I,		/* One Wire 2 Interrupt */
+	CPCAP_REG_OW2IE,	/* One Wire 2 Interrupt Enable */
+	CPCAP_REG_OW2,		/* One Wire 2 Control */
+	CPCAP_REG_OW3C,		/* One Wire 3 Command */
+	CPCAP_REG_OW3D,		/* One Wire 3 Data */
+	CPCAP_REG_OW3I,		/* One Wire 3 Interrupt */
+	CPCAP_REG_OW3IE,	/* One Wire 3 Interrupt Enable */
+	CPCAP_REG_OW3,		/* One Wire 3 Control */
+	CPCAP_REG_GCAIC,	/* GCAI Clock Control */
+	CPCAP_REG_GCAIM,	/* GCAI GPIO Mode */
+	CPCAP_REG_LGDIR,	/* LMR GCAI GPIO Direction */
+	CPCAP_REG_LGPU,		/* LMR GCAI GPIO Pull-up */
+	CPCAP_REG_LGPIN,	/* LMR GCAI GPIO Pin */
+	CPCAP_REG_LGMASK,	/* LMR GCAI GPIO Mask */
+	CPCAP_REG_LDEB,		/* LMR Debounce Settings */
+	CPCAP_REG_LGDET,	/* LMR GCAI Detach Detect */
+	CPCAP_REG_LMISC,	/* LMR Misc Bits */
+	CPCAP_REG_LMACE,	/* LMR Mace IC Support */
+	CPCAP_REG_TEST,         /* Test */
+	CPCAP_REG_ST_TEST1,     /* ST Test 1 */
+
+	CPCAP_REG_END = CPCAP_REG_ST_TEST1, /* End of CPCAP registers. */
+
+	CPCAP_REG_MAX		/* The largest valid register value. */
+	= CPCAP_REG_END,
+
+	CPCAP_REG_SIZE = CPCAP_REG_MAX + 1,
+	CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2,
+};
+
+enum {
+	CPCAP_IOCTL_NUM_TEST__START,
+	CPCAP_IOCTL_NUM_TEST_READ_REG,
+	CPCAP_IOCTL_NUM_TEST_WRITE_REG,
+	CPCAP_IOCTL_NUM_TEST__END,
+
+	CPCAP_IOCTL_NUM_ADC__START,
+	CPCAP_IOCTL_NUM_ADC_PHASE,
+	CPCAP_IOCTL_NUM_ADC__END,
+
+	CPCAP_IOCTL_NUM_BATT__START,
+	CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE,
+	CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC,
+	CPCAP_IOCTL_NUM_BATT_ATOD_SYNC,
+	CPCAP_IOCTL_NUM_BATT_ATOD_READ,
+	CPCAP_IOCTL_NUM_BATT__END,
+
+	CPCAP_IOCTL_NUM_UC__START,
+	CPCAP_IOCTL_NUM_UC_MACRO_START,
+	CPCAP_IOCTL_NUM_UC_MACRO_STOP,
+	CPCAP_IOCTL_NUM_UC_GET_VENDOR,
+	CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE,
+	CPCAP_IOCTL_NUM_UC__END,
+
+	CPCAP_IOCTL_NUM_RTC__START,
+	CPCAP_IOCTL_NUM_RTC_COUNT,
+	CPCAP_IOCTL_NUM_RTC__END,
+
+	CPCAP_IOCTL_NUM_ACCY__START,
+	CPCAP_IOCTL_NUM_ACCY_WHISPER,
+	CPCAP_IOCTL_NUM_ACCY__END,
+
+	CPCAP_IOCTL_NUM_AUDIO_PWR__START,
+	CPCAP_IOCTL_NUM_AUDIO_PWR_MODE,
+	CPCAP_IOCTL_NUM_AUDIO_PWR_ENABLE,
+	CPCAP_IOCTL_NUM_AUDIO_PWR__END,
+};
+
+enum cpcap_irqs {
+	CPCAP_IRQ__START,		/* 1st supported interrupt event */
+	CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX, /* High Speed Clock */
+	CPCAP_IRQ_PRIMAC,		/* Primary Macro */
+	CPCAP_IRQ_SECMAC,		/* Secondary Macro */
+	CPCAP_IRQ_LOWBPL,		/* Low Battery Low Threshold */
+	CPCAP_IRQ_SEC2PRI,		/* 2nd Macro to Primary Processor */
+	CPCAP_IRQ_LOWBPH,		/* Low Battery High Threshold  */
+	CPCAP_IRQ_EOL,			/* End of Life */
+	CPCAP_IRQ_TS,			/* Touchscreen */
+	CPCAP_IRQ_ADCDONE,		/* ADC Conversion Complete */
+	CPCAP_IRQ_HS,			/* Headset */
+	CPCAP_IRQ_MB2,			/* Mic Bias2 */
+	CPCAP_IRQ_VBUSOV,		/* Overvoltage Detected */
+	CPCAP_IRQ_RVRS_CHRG,		/* Reverse Charge */
+	CPCAP_IRQ_CHRG_DET,		/* Charger Detected */
+	CPCAP_IRQ_IDFLOAT,		/* ID Float */
+	CPCAP_IRQ_IDGND,		/* ID Ground */
+
+	CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX, /* SE1 Detector */
+	CPCAP_IRQ_SESSEND,		/* Session End */
+	CPCAP_IRQ_SESSVLD,		/* Session Valid */
+	CPCAP_IRQ_VBUSVLD,		/* VBUS Valid */
+	CPCAP_IRQ_CHRG_CURR1,		/* Charge Current Monitor (20mA) */
+	CPCAP_IRQ_CHRG_CURR2,		/* Charge Current Monitor (250mA) */
+	CPCAP_IRQ_RVRS_MODE,		/* Reverse Current Limit */
+	CPCAP_IRQ_ON,			/* On Signal */
+	CPCAP_IRQ_ON2,			/* On 2 Signal */
+	CPCAP_IRQ_CLK,			/* 32k Clock Transition */
+	CPCAP_IRQ_1HZ,			/* 1Hz Tick */
+	CPCAP_IRQ_PTT,			/* Push To Talk */
+	CPCAP_IRQ_SE0CONN,		/* SE0 Condition */
+	CPCAP_IRQ_CHRG_SE1B,		/* CHRG_SE1B Pin */
+	CPCAP_IRQ_UART_ECHO_OVERRUN,	/* UART Buffer Overflow */
+	CPCAP_IRQ_EXTMEMHD,		/* External MEMHOLD */
+
+	CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX, /* Warm Start */
+	CPCAP_IRQ_SYSRSTR,		/* System Restart */
+	CPCAP_IRQ_SOFTRST,		/* Soft Reset */
+	CPCAP_IRQ_DIEPWRDWN,		/* Die Temperature Powerdown */
+	CPCAP_IRQ_DIETEMPH,		/* Die Temperature High */
+	CPCAP_IRQ_PC,			/* Power Cut */
+	CPCAP_IRQ_OFLOWSW,		/* Stopwatch Overflow */
+	CPCAP_IRQ_TODA,			/* TOD Alarm */
+	CPCAP_IRQ_OPT_SEL_DTCH,		/* Detach Detect */
+	CPCAP_IRQ_OPT_SEL_STATE,	/* State Change */
+	CPCAP_IRQ_ONEWIRE1,		/* Onewire 1 Block */
+	CPCAP_IRQ_ONEWIRE2,		/* Onewire 2 Block */
+	CPCAP_IRQ_ONEWIRE3,		/* Onewire 3 Block */
+	CPCAP_IRQ_UCRESET,		/* Microcontroller Reset */
+	CPCAP_IRQ_PWRGOOD,		/* BP Turn On */
+	CPCAP_IRQ_USBDPLLCLK,		/* USB DPLL Status */
+
+	CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX, /* DP Line */
+	CPCAP_IRQ_DMI,			/* DM Line */
+	CPCAP_IRQ_UCBUSY,		/* Microcontroller Busy */
+	CPCAP_IRQ_GCAI_CURR1,		/* Charge Current Monitor (65mA) */
+	CPCAP_IRQ_GCAI_CURR2,		/* Charge Current Monitor (600mA) */
+	CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR,/* SLIMbus Retransmit Error */
+	CPCAP_IRQ_BATTDETB,		/* Battery Presence Detected */
+	CPCAP_IRQ_PRIHALT,		/* Primary Microcontroller Halt */
+	CPCAP_IRQ_SECHALT,		/* Secondary Microcontroller Halt */
+	CPCAP_IRQ_CC_CAL,		/* CC Calibration */
+
+	CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX, /* Prim ROM Rd Macro Int */
+	CPCAP_IRQ_UC_PRIRAMW,		/* Primary RAM Write Macro Int */
+	CPCAP_IRQ_UC_PRIRAMR,		/* Primary RAM Read Macro Int */
+	CPCAP_IRQ_UC_USEROFF,		/* USEROFF Macro Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_4,	/* Primary Macro 4 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_5,	/* Primary Macro 5 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_6,	/* Primary Macro 6 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_7,	/* Primary Macro 7 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_8,	/* Primary Macro 8 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_9,	/* Primary Macro 9 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_10,	/* Primary Macro 10 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_11,	/* Primary Macro 11 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_12,	/* Primary Macro 12 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_13,	/* Primary Macro 13 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_14,	/* Primary Macro 14 Interrupt */
+	CPCAP_IRQ_UC_PRIMACRO_15,	/* Primary Macro 15 Interrupt */
+	CPCAP_IRQ__NUM			/* Number of allocated events */
+};
+
+enum cpcap_adc_bank0 {
+	CPCAP_ADC_AD0_BATTDETB,
+	CPCAP_ADC_BATTP,
+	CPCAP_ADC_VBUS,
+	CPCAP_ADC_AD3,
+	CPCAP_ADC_BPLUS_AD4,
+	CPCAP_ADC_CHG_ISENSE,
+	CPCAP_ADC_BATTI_ADC,
+	CPCAP_ADC_USB_ID,
+
+	CPCAP_ADC_BANK0_NUM,
+};
+
+enum cpcap_adc_bank1 {
+	CPCAP_ADC_AD8,
+	CPCAP_ADC_AD9,
+	CPCAP_ADC_LICELL,
+	CPCAP_ADC_HV_BATTP,
+	CPCAP_ADC_TSX1_AD12,
+	CPCAP_ADC_TSX2_AD13,
+	CPCAP_ADC_TSY1_AD14,
+	CPCAP_ADC_TSY2_AD15,
+
+	CPCAP_ADC_BANK1_NUM,
+};
+
+enum cpcap_adc_format {
+	CPCAP_ADC_FORMAT_RAW,
+	CPCAP_ADC_FORMAT_PHASED,
+	CPCAP_ADC_FORMAT_CONVERTED,
+};
+
+enum cpcap_adc_timing {
+	CPCAP_ADC_TIMING_IMM,
+	CPCAP_ADC_TIMING_IN,
+	CPCAP_ADC_TIMING_OUT,
+};
+
+enum cpcap_adc_type {
+	CPCAP_ADC_TYPE_BANK_0,
+	CPCAP_ADC_TYPE_BANK_1,
+	CPCAP_ADC_TYPE_BATT_PI,
+};
+
+enum cpcap_bank {
+	CPCAP_BANK_PRIMARY,
+	CPCAP_BANK_SECONDARY,
+};
+
+enum cpcap_standby {
+	CPCAP_PRISTANDBY = 0x01,
+	CPCAP_SECSTANDBY = 0x02,
+};
+
+enum cpcap_macro {
+	CPCAP_MACRO_ROMR,
+	CPCAP_MACRO_RAMW,
+	CPCAP_MACRO_RAMR,
+	CPCAP_MACRO_USEROFF,
+	CPCAP_MACRO_4,
+	CPCAP_MACRO_5,
+	CPCAP_MACRO_6,
+	CPCAP_MACRO_7,
+	CPCAP_MACRO_8,
+	CPCAP_MACRO_9,
+	CPCAP_MACRO_10,
+	CPCAP_MACRO_11,
+	CPCAP_MACRO_12,
+	CPCAP_MACRO_13,
+	CPCAP_MACRO_14,
+	CPCAP_MACRO_15,
+
+	CPCAP_MACRO__END,
+};
+
+enum cpcap_vendor {
+	CPCAP_VENDOR_ST,
+	CPCAP_VENDOR_TI,
+};
+
+enum cpcap_revision {
+	CPCAP_REVISION_1_0 = 0x08,
+	CPCAP_REVISION_1_1 = 0x09,
+	CPCAP_REVISION_2_0 = 0x10,
+	CPCAP_REVISION_2_1 = 0x11,
+};
+
+enum cpcap_batt_usb_model {
+	CPCAP_BATT_USB_MODEL_NONE,
+	CPCAP_BATT_USB_MODEL_USB,
+	CPCAP_BATT_USB_MODEL_FACTORY,
+};
+
+struct cpcap_spi_init_data {
+	enum cpcap_reg reg;
+	unsigned short data;
+};
+
+struct cpcap_adc_ato {
+	unsigned short ato_in;
+	unsigned short atox_in;
+	unsigned short adc_ps_factor_in;
+	unsigned short atox_ps_factor_in;
+	unsigned short ato_out;
+	unsigned short atox_out;
+	unsigned short adc_ps_factor_out;
+	unsigned short atox_ps_factor_out;
+	unsigned short ichrg_sense_res;
+};
+
+struct cpcap_display_led {
+	unsigned int display_reg;
+	unsigned int display_mask;
+	unsigned int display_on;
+	unsigned int display_off;
+	unsigned int display_init;
+	unsigned int poll_intvl;
+	unsigned int zone0;
+	unsigned int zone1;
+	unsigned int zone2;
+	unsigned int zone3;
+	unsigned int zone4;
+};
+
+struct cpcap_button_led {
+	unsigned int button_reg;
+	unsigned int button_mask;
+	unsigned int button_on;
+	unsigned int button_off;
+};
+
+struct cpcap_kpad_led {
+	unsigned int kpad_reg;
+	unsigned int kpad_mask;
+	unsigned int kpad_on;
+	unsigned int kpad_off;
+};
+
+struct cpcap_rgb_led {
+	unsigned int rgb_reg;
+	unsigned int rgb_mask;
+	unsigned int rgb_on;
+	unsigned int rgb_off;
+};
+struct cpcap_als_data {
+	unsigned short lux_max;
+	unsigned short lux_min;
+	unsigned short als_max;
+	unsigned short als_min;
+};
+
+struct cpcap_leds {
+	struct cpcap_display_led display_led;
+	struct cpcap_button_led button_led;
+	struct cpcap_kpad_led kpad_led;
+	struct cpcap_rgb_led rgb_led;
+	struct cpcap_als_data als_data;
+};
+
+struct cpcap_batt_data {
+	int status;
+	int health;
+	int present;
+	int capacity;
+	int batt_volt;
+	int batt_temp;
+	int batt_full_capacity;
+	int batt_capacity_one;
+	int cycle_count;
+	int timestamp;
+	unsigned long charge_cycle_counter;
+	unsigned char charge_cycle_counter_percentage;
+};
+
+struct cpcap_batt_ac_data {
+	int online;
+};
+
+struct cpcap_batt_usb_data {
+	int online;
+	int current_now;
+	enum cpcap_batt_usb_model model;
+};
+
+struct cpcap_rtc_time_cnt {
+	struct rtc_time time;
+	unsigned short count;
+};
+
+struct cpcap_device;
+
+#ifdef __KERNEL__
+struct cpcap_platform_data {
+	struct cpcap_spi_init_data *init;
+	int init_len;
+	unsigned short *regulator_mode_values;
+	unsigned short *regulator_off_mode_values;
+	struct regulator_init_data *regulator_init;
+	struct cpcap_adc_ato *adc_ato;
+	struct cpcap_leds *leds;
+	void (*ac_changed)(struct power_supply *,
+			   struct cpcap_batt_ac_data *);
+	void (*batt_changed)(struct power_supply *,
+			     struct cpcap_batt_data *);
+	void (*usb_changed)(struct power_supply *,
+			    struct cpcap_batt_usb_data *);
+	u16 hwcfg[CPCAP_HWCFG_NUM];
+	unsigned short is_umts;
+	unsigned int irq_gpio;
+};
+
+struct cpcap_adc_request {
+	enum cpcap_adc_format format;
+	enum cpcap_adc_timing timing;
+	enum cpcap_adc_type type;
+	int status;
+	int result[CPCAP_ADC_BANK0_NUM];
+	void (*callback)(struct cpcap_device *, void *);
+	void *callback_param;
+
+	/* Used in case of sync requests */
+	struct completion completion;
+};
+#endif
+
+struct cpcap_adc_us_request {
+	enum cpcap_adc_format format;
+	enum cpcap_adc_timing timing;
+	enum cpcap_adc_type type;
+	int status;
+	int result[CPCAP_ADC_BANK0_NUM];
+};
+
+struct cpcap_adc_phase {
+	signed char offset_batti;
+	unsigned char slope_batti;
+	signed char offset_chrgi;
+	unsigned char slope_chrgi;
+	signed char offset_battp;
+	unsigned char slope_battp;
+	signed char offset_bp;
+	unsigned char slope_bp;
+	signed char offset_battt;
+	unsigned char slope_battt;
+	signed char offset_chrgv;
+	unsigned char slope_chrgv;
+};
+
+struct cpcap_regacc {
+	unsigned short reg;
+	unsigned short value;
+	unsigned short mask;
+};
+
+/*
+ * Gets the contents of the specified cpcap register.
+ *
+ * INPUTS: The register number in the cpcap driver's format.
+ *
+ * OUTPUTS: The command writes the register data back to user space at the
+ * location specified, or it may return an error code.
+ */
+#define CPCAP_IOCTL_GET_RTC_TIME_COUNTER \
+	_IOR(0, CPCAP_IOCTL_NUM_RTC_COUNT, struct cpcap_rtc_time_cnt)
+
+#define CPCAP_IOCTL_TEST_READ_REG \
+	_IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*)
+
+/*
+ * Writes the specifed cpcap register.
+ *
+ * This function writes the specified cpcap register with the specified
+ * data.
+ *
+ * INPUTS: The register number in the cpcap driver's format and the data to
+ * write to that register.
+ *
+ * OUTPUTS: The command has no output other than the returned error code for
+ * the ioctl() call.
+ */
+#define CPCAP_IOCTL_TEST_WRITE_REG \
+	_IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*)
+
+#define CPCAP_IOCTL_ADC_PHASE \
+	_IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*)
+
+#define CPCAP_IOCTL_BATT_DISPLAY_UPDATE \
+	_IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*)
+
+#define CPCAP_IOCTL_BATT_ATOD_ASYNC \
+	_IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*)
+
+#define CPCAP_IOCTL_BATT_ATOD_SYNC \
+	_IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*)
+
+#define CPCAP_IOCTL_BATT_ATOD_READ \
+	_IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*)
+
+
+#define CPCAP_IOCTL_UC_MACRO_START \
+	_IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro)
+
+#define CPCAP_IOCTL_UC_MACRO_STOP \
+	_IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro)
+
+#define CPCAP_IOCTL_UC_GET_VENDOR \
+	_IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor)
+
+#define CPCAP_IOCTL_UC_SET_TURBO_MODE \
+	_IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short)
+
+#define CPCAP_IOCTL_ACCY_WHISPER \
+	_IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, unsigned long)
+
+#define CPCAP_IOCTL_AUDIO_PWR_MODE \
+	_IOW(0, CPCAP_IOCTL_NUM_AUDIO_PWR_MODE,  unsigned short)
+
+#define CPCAP_IOCTL_AUDIO_PWR_ENABLE \
+	_IOW(0, CPCAP_IOCTL_NUM_AUDIO_PWR_ENABLE,  unsigned short)
+
+#ifdef __KERNEL__
+struct cpcap_device {
+	struct spi_device	*spi;
+	enum cpcap_vendor       vendor;
+	enum cpcap_revision     revision;
+	void			*keydata;
+	struct platform_device  *regulator_pdev[CPCAP_NUM_REGULATORS];
+	void			*irqdata;
+	void			*adcdata;
+	void			*battdata;
+	void			*ucdata;
+	void			(*h2w_new_state)(int);
+};
+
+static inline void cpcap_set_keydata(struct cpcap_device *cpcap, void *data)
+{
+	cpcap->keydata = data;
+}
+
+static inline void *cpcap_get_keydata(struct cpcap_device *cpcap)
+{
+	return cpcap->keydata;
+}
+
+int cpcap_regacc_write(struct cpcap_device *cpcap, enum cpcap_reg reg,
+		       unsigned short value, unsigned short mask);
+
+int cpcap_regacc_read(struct cpcap_device *cpcap, enum cpcap_reg reg,
+		      unsigned short *value_ptr);
+
+int cpcap_regacc_init(struct cpcap_device *cpcap);
+
+void cpcap_broadcast_key_event(struct cpcap_device *cpcap,
+			       unsigned int code, int value);
+
+int cpcap_irq_init(struct cpcap_device *cpcap);
+
+void cpcap_irq_shutdown(struct cpcap_device *cpcap);
+
+int cpcap_irq_register(struct cpcap_device *cpcap, enum cpcap_irqs irq,
+		       void (*cb_func) (enum cpcap_irqs, void *), void *data);
+
+int cpcap_irq_free(struct cpcap_device *cpcap, enum cpcap_irqs irq);
+
+int cpcap_irq_get_data(struct cpcap_device *cpcap, enum cpcap_irqs irq,
+		       void **data);
+
+int cpcap_irq_clear(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
+
+int cpcap_irq_mask(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
+
+int cpcap_irq_unmask(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
+
+int cpcap_irq_mask_get(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
+
+int cpcap_irq_sense(struct cpcap_device *cpcap, enum cpcap_irqs int_event,
+		    unsigned char clear);
+
+int cpcap_adc_sync_read(struct cpcap_device *cpcap,
+			struct cpcap_adc_request *request);
+
+int cpcap_adc_async_read(struct cpcap_device *cpcap,
+			 struct cpcap_adc_request *request);
+
+void cpcap_adc_phase(struct cpcap_device *cpcap, struct cpcap_adc_phase *phase);
+
+void cpcap_batt_set_ac_prop(struct cpcap_device *cpcap, int online);
+
+void cpcap_batt_set_usb_prop_online(struct cpcap_device *cpcap, int online,
+				    enum cpcap_batt_usb_model model);
+
+void cpcap_batt_set_usb_prop_curr(struct cpcap_device *cpcap,
+				  unsigned int curr);
+
+int cpcap_uc_start(struct cpcap_device *cpcap, enum cpcap_macro macro);
+
+int cpcap_uc_stop(struct cpcap_device *cpcap, enum cpcap_macro macro);
+
+unsigned char cpcap_uc_status(struct cpcap_device *cpcap,
+			      enum cpcap_macro macro);
+
+int cpcap_disable_offmode_wakeups(bool disable);
+
+#ifdef CONFIG_PM_DBG_DRV
+void cpcap_irq_pm_dbg_suspend(void);
+void cpcap_irq_pm_dbg_resume(void);
+int cpcap_uc_ram_write(struct cpcap_device *cpcap, unsigned short address,
+		     unsigned short num_words, unsigned short *data);
+
+int cpcap_uc_ram_read(struct cpcap_device *cpcap, unsigned short address,
+		    unsigned short num_words, unsigned short *data);
+#endif /* CONFIG_PM_DBG_DRV */
+
+#define  cpcap_driver_register platform_driver_register
+#define  cpcap_driver_unregister platform_driver_unregister
+
+int cpcap_device_register(struct platform_device *pdev);
+int cpcap_device_unregister(struct platform_device *pdev);
+
+#endif /* __KERNEL__ */
+#endif /* _LINUX_SPI_CPCAP_H */