Merge branch 'android-omap-minnow-3.10-lollipop-wear-release' of https://android.googlesource.com/kernel/omap into mattis_devmattis_dev

Change-Id: I46165dd7747b9b6289eb44cb96cbef2de46c10ba

12 files changed, 159 insertions, 50 deletions

diff --git a/arch/arm/boot/dts/omap3-minnow.dtsi b/arch/arm/boot/dts/omap3-minnow.dtsi
index aaadebb253b..efdb2d53f9a 100644
--- a/arch/arm/boot/dts/omap3-minnow.dtsi
+++ b/arch/arm/boot/dts/omap3-minnow.dtsi
@@ -7,6 +7,8 @@
  */
 /* reserve memory for ram_console */
 /memreserve/ 0x83000000 0x20000; /* IMAGE_DOWN_LOAD_ADDR */
+/memreserve/ 0x83020000 0x16000; /* OMAP_SECURE_RAM_STORAGE_ADDR */
+/memreserve/ 0x83036000 0x9000;  /* OMAP3_SECURE_RAM_CTX_ADDR */
 
 /include/ "omap36xx.dtsi"
 
@@ -93,6 +95,8 @@
 		//pixel_format = <1>;
 		//hs_clk = <90000000 150000000>;        /* min max*/
 		//lp_clk = <7000000 9000000>;   /* min max*/
+		/* panel dimensions (width and height) in um */
+		panel_size_um = <39744 36020>;
 		pinctrl-names = "viopulldown", "viooutput";
 		pinctrl-0 = <&display_vddio_pulldown>;
 		pinctrl-1 = <&display_vddio_output>;
@@ -200,17 +204,21 @@
 		mot,mic_bias3_en = <&gpio3 20 0>; /* gpio-084 */
 	};
 
-	omap_pimic {
+	regulators {
+		compatible = "simple-bus";
+
 		omap_tps65912_dcdc1: omap_vdd1 {
 			compatible = "ti,omap-tps65912-dcdc1";
 			ti,boot-voltage-micro-volts = <1275000>;
 			ti,vp = <&vp_mpu>;
+			regulator-name = "omap_vdd1";
 		};
 
 		omap_tps65912_dcdc4: omap_vdd2 {
 			compatible = "ti,omap-tps65912-dcdc4";
 			ti,boot-voltage-micro-volts = <1200000>;
 			ti,vp = <&vp_core>;
+			regulator-name = "omap_vdd2";
 		};
 	};
 
@@ -272,10 +280,6 @@
 	vc_mpu{
 		ti,master-channel;
 	};
-
-	vc_core{
-		ti,use-master-slave-addr;
-	};
 };
 
 &glbl_prm {
@@ -309,6 +313,8 @@
 };
 
 &i2c2 {
+
+	clock-frequency = <400000>;
 	m4sensorhub@39 {
 		compatible = "mot,m4sensorhub";
 		status = "ok";
@@ -346,11 +352,52 @@
 		interrupts = <12 0>;		/* gpio-140 IRQ */
 		maxim,malicious_supply = "ac";
 		maxim,enable_por_init;
+
+		/* This is the default battery profile attributes used by max17xxxx driver */
+		/* It is used when batt-id isn't defined in /chosen as batt-id.  The       */
+		/* Value is originally used under the assumption that this is an LG battery*/
+		/* Otherwise, the driver will either pick SNN5951A or SNN5950A as defined  */
+		/* Right below it.  */
 		maxim,configuration {
 			/* Required properties */
+			version		= /bits/ 16 <0x0001>;
+			config		= /bits/ 16 <0x6254>;	/* Tex = 0, Ss = Aen = TS = Ten = ETHRM = 1 */
+			full_soc_thresh	= /bits/ 16 <0x5F00>;	/* app note constant */
+			design_cap	= /bits/ 16 <606>;	/* in 5uVh/Rsns = 0.5 mAh */
+			ichgt_term	= /bits/ 16 <0x0066>;	/* battery attribute */
+			learn_cfg	= /bits/ 16 <0x2606>;	/* app note constant */
+			filter_cfg	= /bits/ 16 <0x87A4>;	/* app note constant */
+			relax_cfg	= /bits/ 16 <0x043B>;	/* Load = 5 mA, dV = 3.7 mV, dT = 6 mins */
+			fullcap		= /bits/ 16 <662>;	/* in 5uVh/Rsns = 0.5 mAh */
+			fullcapnom	= /bits/ 16 <662>;	/* in 5uVh/Rsns = 0.5 mAh */
+			qrtbl00		= /bits/ 16 <0x1B94>;	/* battery attribute */
+			qrtbl10		= /bits/ 16 <0x0E94>;	/* battery attribute */
+			qrtbl20		= /bits/ 16 <0x0594>;	/* battery attribute */
+			qrtbl30		= /bits/ 16 <0x0294>;	/* battery attribute */
+			rcomp0 		= /bits/ 16 <0x0052>;	/* battery attribute */
+			tcompc0		= /bits/ 16 <0x333A>;	/* battery attribute */
+			maxim,cell-char-tbl = /bits/ 16 <	/* battery attribute */
+				0x9cf0 0xa310 0xb180 0xb360 0xb6a0 0xb6e0
+				0xba10 0xbb10 0xbbd0 0xbc10 0xc200 0xc250
+				0xc7c0 0xc820 0xd050 0xd710 0x0140 0x0110
+				0x0210 0x02c0 0x1000 0x0a00 0x06c0 0x31a0
+				0x0af0 0x1170 0x0cb0 0x08d0 0x0aa0 0x0880
+				0x07b0 0x07b0 0x0100 0x0100 0x0100 0x0100
+				0x0100 0x0100 0x0100 0x0100 0x0100 0x0100
+				0x0100 0x0100 0x0100 0x0100 0x0100 0x0100
+			>;
+			/* Optional properties */
+			tgain		= /bits/ 16 <0xE71C>;	/* thermistor attribute */
+			toff		= /bits/ 16 <0x251A>;	/* thermistor attribute */
+		};
+
+		/* LG Battery profile */
+		maxim,configuration-SNN5951A {
+			/* Required properties */
+			version		= /bits/ 16 <0x0001>;
 			config		= /bits/ 16 <0x6254>;	/* Tex = 0, Ss = Aen = TS = Ten = ETHRM = 1 */
 			full_soc_thresh	= /bits/ 16 <0x5F00>;	/* app note constant */
-			design_cap	= /bits/ 16 <662>;	/* in 5uVh/Rsns = 0.5 mAh */
+			design_cap	= /bits/ 16 <606>;	/* in 5uVh/Rsns = 0.5 mAh */
 			ichgt_term	= /bits/ 16 <0x0066>;	/* battery attribute */
 			learn_cfg	= /bits/ 16 <0x2606>;	/* app note constant */
 			filter_cfg	= /bits/ 16 <0x87A4>;	/* app note constant */
@@ -377,6 +424,40 @@
 			tgain		= /bits/ 16 <0xE71C>;	/* thermistor attribute */
 			toff		= /bits/ 16 <0x251A>;	/* thermistor attribute */
 		};
+		/* Lishen battery profile */
+		maxim,configuration-SNN5950A {
+			/* Required properties */
+			version		= /bits/ 16 <0x0001>;
+			config          = /bits/ 16 <0x6254>;   /* Tex = 0, TS = Ten = ETHRM = 1,  Aen = 1 */
+			full_soc_thresh = /bits/ 16 <0x5F00>;   /* app note constant */
+			design_cap      = /bits/ 16 <662>;      /* in 5uVh/Rsns = 0.5 mAh */
+			ichgt_term      = /bits/ 16 <0x0066>;   /* battery attribute */
+			learn_cfg       = /bits/ 16 <0x2606>;   /* app note constant */
+			filter_cfg      = /bits/ 16 <0x87A4>;   /* app note constant */
+			relax_cfg       = /bits/ 16 <0x203B>;   /* Load = 5 mA, dV = 3.7 mV, dT = 6 mins */
+			fullcap         = /bits/ 16 <662>;      /* in 5uVh/Rsns = 0.5 mAh */
+			fullcapnom      = /bits/ 16 <662>;      /* in 5uVh/Rsns = 0.5 mAh */
+			qrtbl00         = /bits/ 16 <0x069A>;   /* battery attribute */
+			qrtbl10         = /bits/ 16 <0x0398>;   /* battery attribute */
+			qrtbl20         = /bits/ 16 <0x0298>;   /* battery attribute */
+			qrtbl30         = /bits/ 16 <0x0296>;   /* battery attribute */
+			rcomp0          = /bits/ 16 <0x003C>;   /* battery attribute */
+			tcompc0         = /bits/ 16 <0x231C>;   /* battery attribute */
+			maxim,cell-char-tbl = /bits/ 16 <       /* battery attribute */
+				0x9f80 0xa030 0xb220 0xb440 0xb890 0xb910
+				0xba10 0xba40 0xbf10 0xbf60 0xc2d0 0xc5e0
+				0xc640 0xcc90 0xd520 0xd780 0x05d0 0x00e0
+				0x01e0 0x03a0 0x08e0 0x1000 0x4000 0x1670
+				0x23d0 0x0df0 0x0a70 0x0aa0 0x06f0 0x0790
+				0x06b0 0x06b0 0x0100 0x0100 0x0100 0x0100
+				0x0100 0x0100 0x0100 0x0100 0x0100 0x0100
+				0x0100 0x0100 0x0100 0x0100 0x0100 0x0100
+			>;
+			/* Optional properties */
+			tgain           = /bits/ 16 <0xE71C>;   /* thermistor attribute */
+			toff            = /bits/ 16 <0x251A>;   /* thermistor attribute */
+		};
+
 		maxim,temp-conv {
 			start	= /bits/ 16 <(-20)>;	/* in degrees C */
 			result	= /bits/ 16 <
diff --git a/arch/arm/configs/minnow_defconfig b/arch/arm/configs/minnow_defconfig
index 38ae97a68a7..fe129184caf 100644
--- a/arch/arm/configs/minnow_defconfig
+++ b/arch/arm/configs/minnow_defconfig
@@ -1154,6 +1154,7 @@ CONFIG_MOT_UTAG=y
 CONFIG_BQ5105X_CTRL=y
 CONFIG_BQ5105X_DETECT=y
 CONFIG_WAKEUP_SOURCE_NOTIFY=y
+CONFIG_ALS_WHILE_CHARGING=y
 # CONFIG_C2PORT is not set
 
 #
@@ -1399,7 +1400,7 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_CM109 is not set
-# CONFIG_INPUT_UINPUT is not set
+CONFIG_INPUT_UINPUT=y
 # CONFIG_INPUT_GPIO is not set
 # CONFIG_INPUT_PCF8574 is not set
 # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index e823edd05eb..50d8b4587f6 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -137,6 +137,10 @@ DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
 		   OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
 		   CLK_DIVIDER_ONE_BASED, NULL);
 
+/* placeholder for ops substitution */
+static struct clk_ops dpll3_m2_ck_subops = {
+};
+
 static struct clk core_ck;
 
 static const char *core_ck_parent_names[] = {
@@ -3566,6 +3570,11 @@ int __init omap3xxx_clk_init(void)
 		dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
 		dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
 		dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
+		memcpy(
+		&dpll3_m2_ck_subops, dpll3_m2_ck.ops, sizeof(struct clk_ops));
+
+		dpll3_m2_ck_subops.set_rate = omap3_core_dpll_m2_set_rate;
+		dpll3_m2_ck.ops = &dpll3_m2_ck_subops;
 	}
 
 	/*
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index eb69acf2101..1fc3b607c7d 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -55,15 +55,16 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct omap_sdrc_params *sdrc_cs0;
 	struct omap_sdrc_params *sdrc_cs1;
 	int ret;
-	unsigned long clkrate;
+	unsigned long clkrate, flags;
 
 	if (!clk || !rate)
 		return -EINVAL;
 
-	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+	validrate = clk_round_rate(hw->clk, rate);
 	if (validrate != rate)
 		return -EINVAL;
 
+	new_div = parent_rate / validrate;
 	sdrcrate = __clk_get_rate(sdrc_ick_p);
 	clkrate = __clk_get_rate(hw->clk);
 	if (rate > clkrate)
@@ -101,6 +102,7 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
 			 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 			 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 
+	local_irq_save(flags);
 	if (sdrc_cs1)
 		omap3_configure_core_dpll(
 				  new_div, unlock_dll, c, rate > clkrate,
@@ -114,6 +116,7 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
 				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 				  0, 0, 0, 0);
+	local_irq_restore(flags);
 	return 0;
 }
 
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index ab5ec4b28ab..a7da7ccd1a1 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -92,7 +92,7 @@ struct omap3_scratchpad_sdrc_block {
 	u32 block_size;
 };
 
-void *omap3_secure_ram_storage;
+phys_addr_t omap3_secure_ram_context;
 
 /*
  * This is used to store ARM registers in SDRAM before attempting
@@ -360,7 +360,7 @@ void omap3_save_scratchpad_contents(void)
 		scratchpad_contents.secure_ram_restore_ptr = 0x0;
 	else
 		scratchpad_contents.secure_ram_restore_ptr =
-			(u32) __pa(omap3_secure_ram_storage);
+			(u32) omap3_secure_ram_context;
 	scratchpad_contents.sdrc_module_semaphore = 0x0;
 	scratchpad_contents.prcm_block_offset = 0x2C;
 	scratchpad_contents.sdrc_block_offset = 0x64;
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index b970440cffc..55b24c32099 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -58,10 +58,7 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
 /* Allocate the memory to save secure ram */
 int __init omap_secure_ram_reserve_memblock(void)
 {
-	u32 size = OMAP_SECURE_RAM_STORAGE;
-
-	size = ALIGN(size, SECTION_SIZE);
-	omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
+	omap_secure_memblock_base = OMAP_SECURE_RAM_STORAGE_ADDR;
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 0e729170c46..dd894db8599 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -28,6 +28,7 @@
 
 /* Maximum Secure memory storage size */
 #define OMAP_SECURE_RAM_STORAGE	(88 * SZ_1K)
+#define OMAP_SECURE_RAM_STORAGE_ADDR	0x83020000
 
 /* Secure low power HAL API index */
 #define OMAP4_HAL_SAVESECURERAM_INDEX	0x1a
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index b5dff42606c..ea5a306d1f1 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,8 +38,16 @@
 #include "pm.h"
 #include "pm-debug-regs.h"
 
+/* enable_off_mode is the runtime flag for enable/disable of offmode */
 u32 enable_off_mode;
 
+/*
+ * global_disable_off_mode supercedes enable_off_mode and keeps
+ * offmode disabled as long as it is set
+ */
+bool global_disable_off_mode = 1;
+module_param(global_disable_off_mode, bool, 0644);
+
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -236,9 +244,13 @@ static int option_set(void *data, u64 val)
 {
 	u32 *option = data;
 
-	*option = val;
-
 	if (option == &enable_off_mode) {
+		if (global_disable_off_mode) {
+			pr_warn("Disable global_disable_off_mode "
+				"before enabling off mode");
+			return -EINVAL;
+		}
+
 		if (val)
 			omap_pm_enable_off_mode();
 		else
@@ -247,6 +259,8 @@ static int option_set(void *data, u64 val)
 			omap3_pm_off_mode_enable(val);
 	}
 
+	*option = val;
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 303a8d2012b..b2dc18a6b82 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -311,13 +311,6 @@ int __init omap2_common_pm_late_init(void)
 		/* Smartreflex device init */
 		omap_devinit_smartreflex();
 
-	} else {
-		struct device_node *np;
-		np = of_find_node_by_name(NULL, "omap_pimic");
-		if (np) {
-			of_platform_populate(np, NULL, NULL, NULL);
-			of_node_put(np);
-		}
 	}
 
 	/* cpufreq dummy device instantiation */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 4f6f52b5215..551db0bb4a6 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -30,7 +30,7 @@ static inline int omap4_idle_init(void)
 }
 #endif
 
-extern void *omap3_secure_ram_storage;
+extern phys_addr_t omap3_secure_ram_context;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(bool in_suspend);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 6f67bfa0b03..bdb2388ef4c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -59,6 +59,10 @@
 
 #include "pad_wkup.h"
 
+#define OMAP3_SECURE_RAM_CTX_ADDR	0x83036000
+
+extern bool global_disable_off_mode;
+
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
 bool suspend_debug;
@@ -133,8 +137,7 @@ static void omap3_save_secure_ram_context(void)
 		 * will hang the system.
 		 */
 		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
-		ret = _omap_save_secure_sram((u32 *)
-				__pa(omap3_secure_ram_storage));
+		ret = _omap_save_secure_sram((u32 *)omap3_secure_ram_context);
 		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 		/* Following is for error tracking, it should not happen */
 		if (ret) {
@@ -667,6 +670,12 @@ void omap3_pm_off_mode_enable(int enable)
 			pwrst->next_state = PWRDM_POWER_RET;
 			pr_warn("%s: Core OFF disabled due to errata i583\n",
 				__func__);
+		} else if (global_disable_off_mode &&
+				pwrst->pwrdm == core_pwrdm &&
+				state == PWRDM_POWER_OFF) {
+			pwrst->next_state = PWRDM_POWER_RET;
+			pr_warn("%s: Core OFF disabled due global disable\n",
+				__func__);
 		} else {
 			pwrst->next_state = state;
 		}
@@ -741,13 +750,14 @@ static void __init pm_errata_configure(void)
 		/* Enable the l2 cache toggling in sleep logic */
 		enable_omap3630_toggle_l2_on_restore();
 
-		if (omap_rev() < OMAP3630_REV_ES1_2)
+		if (omap_rev() < OMAP3630_REV_ES1_2) {
 			pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
 #ifndef CONFIG_DISABLE_OMAP_ERRATA_i583
 			pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 #endif
-		if (meminfo.bank[0].size > 256 * (1024 * 1024))
-			pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+			if (meminfo.bank[0].size > 256 * (1024 * 1024))
+				pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+		}
 
 	} else if (cpu_is_omap34xx()) {
 		pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
@@ -818,8 +828,7 @@ int __init omap3_pm_init(void)
 	omap_pm_suspend = omap3_pm_suspend;
 #endif
 
-	if (omap_pm_get_off_mode())
-		omap3_pm_off_mode_enable(true);
+	omap3_pm_off_mode_enable(omap_pm_get_off_mode());
 
 	arm_pm_idle = omap3_pm_idle;
 	omap3_idle_init();
@@ -850,15 +859,16 @@ int __init omap3_pm_init(void)
 	 * XXX Technically this workaround is only needed if off-mode
 	 * or OSWR is enabled.
 	 */
-	if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
-		clkdm_add_wkdep(per_clkdm, wkup_clkdm);
+
+	/*
+	 * The PER wake dependency is still needed on ES1.2 which
+	 * has fixed i582
+	 */
+	clkdm_add_wkdep(per_clkdm, wkup_clkdm);
 
 	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
-		omap3_secure_ram_storage =
-			kmalloc(0x803F, GFP_KERNEL);
-		if (!omap3_secure_ram_storage)
-			pr_err("Memory allocation failed when allocating for secure sram context\n");
+		omap3_secure_ram_context = OMAP3_SECURE_RAM_CTX_ADDR;
 
 		local_irq_disable();
 
diff --git a/arch/arm/mach-omap2/sdram-toshiba-hynix-numonyx.h b/arch/arm/mach-omap2/sdram-toshiba-hynix-numonyx.h
index c7acdb8312d..fe835c96b7d 100644
--- a/arch/arm/mach-omap2/sdram-toshiba-hynix-numonyx.h
+++ b/arch/arm/mach-omap2/sdram-toshiba-hynix-numonyx.h
@@ -17,43 +17,43 @@
 static struct omap_sdrc_params JEDEC_JESD209A_sdrc_params[] = {
 	[0] = {
 		.rate        = 200000000,
-		.actim_ctrla = 0xE2E1B4C6,
-		.actim_ctrlb = 0x00022228,
+		.actim_ctrla = 0x7ae1b4c6,
+		.actim_ctrlb = 0x00021217,
 		.rfr_ctrl    = 0x0005E602,
 		.mr          = 0x00000032,
 	},
 	[1] = {
 		.rate        = 100000000,
-		.actim_ctrla = 0x7211B485,
-		.actim_ctrlb = 0x00022214,
+		.actim_ctrla = 0x41912286,
+		.actim_ctrlb = 0x0001110c,
 		.rfr_ctrl    = 0x0002DA02,
 		.mr          = 0x00000032,
 	},
 	[2] = {
 		.rate        = 166000000,
-		.actim_ctrla = 0xE2E1B4C6,
-		.actim_ctrlb = 0x00022228,
+		.actim_ctrla = 0x6A9DB4C6,
+		.actim_ctrlb = 0x00021214,
 		.rfr_ctrl    = 0x0004DD02,
 		.mr          = 0x00000032,
 	},
 	[3] = {
 		.rate        = 83000000,
-		.actim_ctrla = 0x7215B485,
-		.actim_ctrlb = 0x00022214,
+		.actim_ctrla = 0x39512286,
+		.actim_ctrlb = 0x0001110C,
 		.rfr_ctrl    = 0x00025602,
 		.mr          = 0x00000032,
 	},
 	[4] = {
 		.rate        = 160000000,
-		.actim_ctrla = 0xBA9DB4C6,
-		.actim_ctrlb = 0x00022220,
+		.actim_ctrla = 0x625DB4C6,
+		.actim_ctrlb = 0x00021213,
 		.rfr_ctrl    = 0x0004AE02,
 		.mr	     = 0x00000032,
 	},
 	[5] = {
 		.rate        = 80000000,
-		.actim_ctrla = 0x49512284,
-		.actim_ctrlb = 0x0001120C,
+		.actim_ctrla = 0x31512284,
+		.actim_ctrlb = 0x0001110C,
 		.rfr_ctrl    = 0x23E02,
 		.mr	     = 0x00000032,
 	},