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authormattis fjallstrom <mattis@acm.org>2015-09-25 16:07:30 -0700
committermattis fjallstrom <mattis@acm.org>2015-09-25 16:07:43 -0700
commitb042f3194965972c7fdc832f210a49a6b5731dea (patch)
treefa5e1b9d8cf2d346183ff25c4e98040775cfcb60
parentd955f0cd9c528ed33d7da0c760f46572381c2039 (diff)
parent0d8625ed51204ad5f2213a7479c44be1b522e602 (diff)
downloadolio-linux-3.10-b042f3194965972c7fdc832f210a49a6b5731dea.tar.xz
olio-linux-3.10-b042f3194965972c7fdc832f210a49a6b5731dea.zip
Merge branch 'android-3.10-bringup' of ssh://internal.oliodevices.com:29418/kernel/omap into android-3.10-bringup
Change-Id: I7ba752884099c9dafe2f336cf787945eeea3a8f1
-rw-r--r--drivers/iio/light/cm3391.c49
-rw-r--r--drivers/video/omap2/displays/panel-ili9342.c62
2 files changed, 75 insertions, 36 deletions
diff --git a/drivers/iio/light/cm3391.c b/drivers/iio/light/cm3391.c
index abe8b8e7f5c..8049446d98a 100644
--- a/drivers/iio/light/cm3391.c
+++ b/drivers/iio/light/cm3391.c
@@ -53,7 +53,7 @@
#define CM3391_CMD_CS_IT_SHIFT 4
#define CM3391_CMD_CS_IT_MASK (BIT(4) | BIT(5) | BIT(6))
-#define CM3391_CMD_CS_IT_DEFAULT (0x01 << CM3391_CMD_CS_IT_SHIFT)
+#define CM3391_CMD_CS_IT_DEFAULT (0x04 << CM3391_CMD_CS_IT_SHIFT)
#define CM3391_CMD_CS_HS_SHIFT BIT(3)
@@ -69,7 +69,8 @@
#define CM3391_THRESHOLD_PERCENT 10 /* 10 percent */
#define CM3391_MLUX_PER_BIT_DEFAULT 550
-#define CM3391_MLUX_PER_BIT_BASE_IT 100000
+#define CM3391_MLUX_PER_BIT_BASE_IT 800000
+
static const struct {
int val;
@@ -90,6 +91,7 @@ static const int CM3391_cs_it_values[] = {
struct cm3391_cs_info {
u32 id;
int regs_bmp;
+ int auto_it_enabled;
int calibscale;
int mlux_per_bit;
int mlux_per_bit_base_it;
@@ -102,8 +104,9 @@ struct cm3391_cs_info {
static struct cm3391_cs_info cm3391_cs_info_default = {
.id = 3391,
.regs_bmp = 0x0F,
- .calibscale = CM3391_CALIBSCALE_DEFAULT,
- .mlux_per_bit = CM3391_MLUX_PER_BIT_DEFAULT,
+ .auto_it_enabled = 0,
+ .calibscale = CM3391_CALIBSCALE_DEFAULT,
+ .mlux_per_bit = CM3391_MLUX_PER_BIT_DEFAULT,
.mlux_per_bit_base_it = CM3391_MLUX_PER_BIT_BASE_IT,
.cs_it_bits = CM3391_cs_it_bits,
.cs_it_values = CM3391_cs_it_values,
@@ -299,6 +302,9 @@ void cm3391_autoit(struct cm3391_chip *chip, u16 als_raw)
int i;
int update;
s32 ret;
+
+ if(!chip->cs_info->auto_it_enabled)
+ return;
cs_it = chip->conf_regs[CM3391_REG_ADDR_CMD];
cs_it &= CM3391_CMD_CS_IT_MASK;
@@ -321,6 +327,7 @@ void cm3391_autoit(struct cm3391_chip *chip, u16 als_raw)
}
if (update) {
+//printk(KERN_INFO "ALS readings are too high/low changing to:%i als_read:%i", i, als_raw)
cs_it = cm3391_cs_it_scales[i].it;
cs_it <<= CM3391_CMD_CS_IT_SHIFT;
@@ -433,7 +440,7 @@ static int cm3391_get_lux(struct cm3391_chip *chip)
cs_it = val * 1000000 + val2;
lux = (__force u64)cs_info->mlux_per_bit;
lux *= cs_info->mlux_per_bit_base_it;
- lux = div_u64(lux, cs_it);
+ lux = div_u64(lux,cs_it);
/* Get als_raw */
ret = i2c_smbus_read_word_data(client, CM3391_REG_ADDR_ALS);
@@ -509,6 +516,34 @@ static int cm3391_write_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
+static ssize_t cm3391_set_enable_auto_it(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t size)
+{
+ int ret;
+ int val;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct cm3391_chip *chip = iio_priv(indio_dev);
+ struct cm3391_cs_info *cs_info = chip->cs_info;
+ ret = sscanf(buf, "%i", &val);
+ if(ret != 1){
+ return -EINVAL;
+ }
+
+ cs_info->auto_it_enabled = val;
+
+ return size;
+}
+
+static ssize_t cm3391_get_enable_auto_it(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct cm3391_chip *chip = iio_priv(indio_dev);
+ struct cm3391_cs_info *cs_info = chip->cs_info;
+ int len;
+ len = sprintf(buf, "%i\n", cs_info->auto_it_enabled);
+ return len;
+}
/**
* cm3391_get_it_available() - Get available CS IT value
@@ -666,8 +701,12 @@ static const struct iio_chan_spec cm3391_channels[] = {
static IIO_DEVICE_ATTR(in_illuminance_integration_time_available,
S_IRUGO, cm3391_get_it_available, NULL, 0);
+static IIO_DEVICE_ATTR(auto_it,
+ S_IRUGO | S_IWUGO, cm3391_get_enable_auto_it, cm3391_set_enable_auto_it, 0);
+
static struct attribute *cm3391_attributes[] = {
&iio_dev_attr_in_illuminance_integration_time_available.dev_attr.attr,
+ &iio_dev_attr_auto_it.dev_attr.attr,
NULL,
};
diff --git a/drivers/video/omap2/displays/panel-ili9342.c b/drivers/video/omap2/displays/panel-ili9342.c
index d79284e7326..9993cc75191 100644
--- a/drivers/video/omap2/displays/panel-ili9342.c
+++ b/drivers/video/omap2/displays/panel-ili9342.c
@@ -394,14 +394,14 @@ static inline void ili9342_init_seq(struct spi_device *spi) {
ili9342_write_data(spi, 0x00);
ili9342_write_cmd(spi, 0xC0);
- ili9342_write_data(spi, 0x16);
- ili9342_write_data(spi, 0x11);
+ ili9342_write_data(spi, 0x0B);
+ ili9342_write_data(spi, 0x09);
ili9342_write_cmd(spi, 0xC1);
- ili9342_write_data(spi, 0x01);
+ ili9342_write_data(spi, 0x12);
ili9342_write_cmd(spi, 0xC5);
- ili9342_write_data(spi, 0xDB);
+ ili9342_write_data(spi, 0xDA);
// RGB color mode
@@ -419,36 +419,36 @@ static inline void ili9342_init_seq(struct spi_device *spi) {
ili9342_write_cmd(spi, 0xE0);
ili9342_write_data(spi, 0x00); //63
- ili9342_write_data(spi, 0x1b); //62
- ili9342_write_data(spi, 0x22); //61
- ili9342_write_data(spi, 0x05); //59
- ili9342_write_data(spi, 0x13); //57
- ili9342_write_data(spi, 0x07); //50
- ili9342_write_data(spi, 0x4c); //43
- ili9342_write_data(spi, 0xa7); //27
- ili9342_write_data(spi, 0x5f); //20
- ili9342_write_data(spi, 0x05); //13
- ili9342_write_data(spi, 0x0b); //06
- ili9342_write_data(spi, 0x09); //04
- ili9342_write_data(spi, 0x32); //02
- ili9342_write_data(spi, 0x36); //01
+ ili9342_write_data(spi, 0x0e); //62
+ ili9342_write_data(spi, 0x17); //61
+ ili9342_write_data(spi, 0x06); //59
+ ili9342_write_data(spi, 0x12); //57
+ ili9342_write_data(spi, 0x06); //50
+ ili9342_write_data(spi, 0x41); //43
+ ili9342_write_data(spi, 0x68); //27
+ ili9342_write_data(spi, 0x58); //20
+ ili9342_write_data(spi, 0x06); //13
+ ili9342_write_data(spi, 0x0f); //06
+ ili9342_write_data(spi, 0x0d); //04
+ ili9342_write_data(spi, 0x34); //02
+ ili9342_write_data(spi, 0x37); //01
ili9342_write_data(spi, 0x0F); //00
ili9342_write_cmd(spi, 0xE1);
- ili9342_write_data(spi, 0x00); //00
- ili9342_write_data(spi, 0x0c); //01
- ili9342_write_data(spi, 0x0d); //02
- ili9342_write_data(spi, 0x05); //04
- ili9342_write_data(spi, 0x11); //06
- ili9342_write_data(spi, 0x06); //13
- ili9342_write_data(spi, 0x30); //20
- ili9342_write_data(spi, 0x58); //27
- ili9342_write_data(spi, 0x44); //43
- ili9342_write_data(spi, 0x08); //50
- ili9342_write_data(spi, 0x14); //57
- ili9342_write_data(spi, 0x0c); //59
- ili9342_write_data(spi, 0x1e); //61
- ili9342_write_data(spi, 0x24); //62
+ ili9342_write_data(spi, 0x08); //00
+ ili9342_write_data(spi, 0x10); //01
+ ili9342_write_data(spi, 0x17); //02
+ ili9342_write_data(spi, 0x06); //04
+ ili9342_write_data(spi, 0x12); //06
+ ili9342_write_data(spi, 0x07); //13
+ ili9342_write_data(spi, 0x37); //20
+ ili9342_write_data(spi, 0x54); //27
+ ili9342_write_data(spi, 0x4e); //43
+ ili9342_write_data(spi, 0x07); //50
+ ili9342_write_data(spi, 0x10); //57
+ ili9342_write_data(spi, 0x0e); //59
+ ili9342_write_data(spi, 0x34); //61
+ ili9342_write_data(spi, 0x36); //62
ili9342_write_data(spi, 0x0F); //63
ili9342_write_cmd(spi, 0x35);